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Thu, 12 Nov 2026 05:18:41 -0800 (PST) Received: from hu-kuldsing-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-375212e7d24sm43798356eec.22.2026.11.12.05.18.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Nov 2026 05:18:41 -0800 (PST) From: Kuldeep Singh Date: Thu, 12 Nov 2026 18:48:17 +0530 Subject: [PATCH v2 1/2] mmc: sdhci-msm: Enable ICE before enabling crypto support X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261112-qcom_ice_pm_enable-v2-1-177e454d6f22@oss.qualcomm.com> References: <20261112-qcom_ice_pm_enable-v2-0-177e454d6f22@oss.qualcomm.com> In-Reply-To: <20261112-qcom_ice_pm_enable-v2-0-177e454d6f22@oss.qualcomm.com> To: Adrian Hunter , Ulf Hansson , Abel Vesa , Manivannan Sadhasivam , "James E.J. Bottomley" , "Martin K. Petersen" , Eric Biggers Cc: Kuldeep Singh , linux-mmc@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, stable@vger.kernel.org X-Mailer: b4 0.15.2 X-Proofpoint-Spam-Info: AW1haW4tMjYxMTEyMDA1MiBTYWx0ZWRfX1fd6kB9tJ8Zl BMbJED4WSs41vs8QZ8UJV4VdtaOxKYDzVTIqKCS8q/dhQnZ4JBEALToLOJuZSoKnEu9CwlAjevF xk2UhIFEUdpDnQwrEWeRu/biD5Gs9xM= X-Proofpoint-ORIG-GUID: DAhMFPNlfAZAzbNjFRXomKFelZLHX183 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTEyMDA1MiBTYWx0ZWRfX1cAEUcRItarP RW1ZtrnMtwM+OXS886slm46eyriYtyBaA5pyQ3CcLtO9h7sAxucFvhgl0+NTgK1csolOBI3dj2y XZe6PYBvIXYkG87gwBonTLugDPypulTuuHy+WI8otDmJV9Xmz9AqS2tiwlz5QXHKO+ffHhLodIg Iawl0Mtgm3Hg2yqISWq1vDvy/0Msd5w0akJmdkM+gAdFUE0z1mgz1SDrwWroZUYWxESDuVzqJ+k GXobZH3C3BIUXAZbRUtCejqdO48OqqjdzNEOwEwY3wuZvn/gf4WznjswTacReQ/ADW6TnPh4iv4 fp4V/skEjH875ATHnVPXFyzQON5SQA76jtmG3a9NrqgyBH3IPAxuiEkT+7r+jGEziWjk1cKnlBH b+ksmjj+HO4CEYE7NDHlt5B4u/tuoe8XQG9WxfLnQ5iRakwyo18GnQBFWseQ8yl3saUCb6oi/og 4N9scOVzWvwyBIBz6wg== X-Proofpoint-GUID: DAhMFPNlfAZAzbNjFRXomKFelZLHX183 X-Authority-Analysis: v=2.4 cv=Vqe2kO2n c=1 sm=1 tr=0 ts=6af5bcb3 cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=jhS48lKipzocA6WHYXAA:9 a=QEXdDO2ut3YA:10 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-12_01,2026-11-11_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 spamscore=0 adultscore=0 bulkscore=0 impostorscore=0 malwarescore=0 phishscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2611040001 definitions=main-2611120052 sdhci-msm currently exposes MMC crypto profile and sets MMC_CAP2_CRYPTO before enabling ICE. This leaves a window where blk-crypto can issue keyslot programming calls before sdhci-msm has explicitly enabled ICE. Enable ICE during the sdhci-msm crypto early init path which ensures ICE is ready before blk-crypto can issue key programming calls. Remove ICE enable call from CQE path, since ICE is now enabled during SDHCI crypto initialization only. Fixes: c7eed31e235c ("mmc: sdhci-msm: Switch to the new ICE API") Cc: stable@vger.kernel.org Signed-off-by: Kuldeep Singh --- drivers/mmc/host/sdhci-msm.c | 21 ++++++--------------- 1 file changed, 6 insertions(+), 15 deletions(-) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 32b1bcba47d6..b3e0356a03ff 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -1928,6 +1928,12 @@ static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host, msm_host->ice = ice; + err = qcom_ice_enable(msm_host->ice); + if (err) { + dev_err(dev, "%s: failed to enable ICE: %d\n", __func__, err); + return err; + } + /* Initialize the blk_crypto_profile */ caps.reg_val = cpu_to_le32(cqhci_readl(cq_host, CQHCI_CCAP)); @@ -1963,12 +1969,6 @@ static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host, return 0; } -static void sdhci_msm_ice_enable(struct sdhci_msm_host *msm_host) -{ - if (msm_host->mmc->caps2 & MMC_CAP2_CRYPTO) - qcom_ice_enable(msm_host->ice); -} - static int sdhci_msm_ice_resume(struct sdhci_msm_host *msm_host) { if (msm_host->mmc->caps2 & MMC_CAP2_CRYPTO) @@ -2141,10 +2141,6 @@ static inline int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host, return 0; } -static inline void sdhci_msm_ice_enable(struct sdhci_msm_host *msm_host) -{ -} - static inline int sdhci_msm_ice_resume(struct sdhci_msm_host *msm_host) { @@ -2182,12 +2178,7 @@ static u32 sdhci_msm_cqe_irq(struct sdhci_host *host, u32 intmask) static void sdhci_msm_cqe_enable(struct mmc_host *mmc) { - struct sdhci_host *host = mmc_priv(mmc); - struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); - struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); - sdhci_cqe_enable(mmc); - sdhci_msm_ice_enable(msm_host); } static void sdhci_msm_cqe_disable(struct mmc_host *mmc, bool recovery) -- 2.34.1