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From: Arun Iyengar via B4 Relay <devnull+aiyengar1990.gmail.com@kernel.org>
To: Will Deacon <will@kernel.org>,
	Robin Murphy <robin.murphy@arm.com>,
	 "Joerg Roedel (AMD)" <joro@8bytes.org>,
	Rob Herring <robh@kernel.org>,
	 Krzysztof Kozlowski <krzk+dt@kernel.org>,
	 Conor Dooley <conor+dt@kernel.org>,
	Heiko Stuebner <heiko@sntech.de>,
	 Niklas Cassel <cassel@kernel.org>
Cc: Pranjal Shrivastava <praan@google.com>,
	 linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev,
	 linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	 linux-rockchip@lists.infradead.org,
	 Sebastian Reichel <sebastian.reichel@collabora.com>,
	 Shawn Lin <shawn.lin@rock-chips.com>,
	Simon Xue <xxm@rock-chips.com>,
	 Finley Xiao <finley.xiao@rock-chips.com>,
	 Arun Iyengar <aiyengar1990@gmail.com>
Subject: [PATCH v2 2/4] iommu/arm-smmu-v3: Enable an optional clock
Date: Thu, 12 Nov 2026 08:20:23 +0000	[thread overview]
Message-ID: <20261112-smmu-v3-pcie-pd-v2-2-3a77bbb6b2c4@gmail.com> (raw)
In-Reply-To: <20261112-smmu-v3-pcie-pd-v2-0-3a77bbb6b2c4@gmail.com>

From: Arun Iyengar <aiyengar1990@gmail.com>

On some platforms the SMMU's clock is controlled by the OS, and without a
consumer the clock framework gates it as unused late in boot. Any later
register access, for example the CR0 write in the shutdown path, then
hangs. This happens on the RK3588 when no PCIe controller keeps the PCIe
MMU-600 clock running.

Get and enable the clock described in the firmware node, if there is
one, and keep it enabled while the driver is bound. Do it first in
probe: the firmware probe may take a reference on the Tegra CMDQV device
that only arm_smmu_impl_probe() releases, so a failure (or deferral)
between the two would leak it. Nodes without a clock and ACPI systems
are not affected.

Signed-off-by: Arun Iyengar <aiyengar1990@gmail.com>
---
 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index 6d4520c47308..d3f42316b0d6 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -12,6 +12,7 @@
 #include <linux/acpi.h>
 #include <linux/acpi_iort.h>
 #include <linux/bitops.h>
+#include <linux/clk.h>
 #include <linux/crash_dump.h>
 #include <linux/delay.h>
 #include <linux/err.h>
@@ -5786,12 +5787,22 @@ static int arm_smmu_device_probe(struct platform_device *pdev)
 	resource_size_t ioaddr;
 	struct arm_smmu_device *smmu;
 	struct device *dev = &pdev->dev;
+	struct clk *clk;
 
 	smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
 	if (!smmu)
 		return -ENOMEM;
 	smmu->dev = dev;
 
+	/*
+	 * Before the firmware probe: it may take a reference on the Tegra
+	 * CMDQV device that only arm_smmu_impl_probe() releases.
+	 */
+	clk = devm_clk_get_optional_enabled(dev, NULL);
+	if (IS_ERR(clk))
+		return dev_err_probe(dev, PTR_ERR(clk),
+				     "failed to enable clock\n");
+
 	if (dev->of_node) {
 		ret = arm_smmu_device_dt_probe(pdev, smmu);
 	} else {

-- 
2.55.0



  parent reply	other threads:[~2026-11-12  8:20 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-12  8:20 [PATCH v2 0/4] iommu/arm-smmu-v3: Keep the clock of the RK3588 PCIe SMMU running Arun Iyengar via B4 Relay
2026-11-12  8:20 ` [PATCH v2 1/4] dt-bindings: iommu: arm,smmu-v3: Allow a clock and a reset Arun Iyengar via B4 Relay
2026-11-12 16:38   ` Sebastian Reichel
2026-11-12  8:20 ` Arun Iyengar via B4 Relay [this message]
2026-11-12  8:20 ` [PATCH v2 3/4] arm64: dts: rockchip: Add the clock of the RK3588 PCIe SMMU Arun Iyengar via B4 Relay
2026-11-12  8:20 ` [PATCH v2 4/4] arm64: dts: rockchip: Add the reset " Arun Iyengar via B4 Relay
2026-11-12 16:33   ` Sebastian Reichel

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