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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: GA1p11qcOizRmaoNvd8MFxZNaoY5EJnKYr6a8MfzN3+S6uqetKzvRClyRFVfFvRIBORitzu9uTwc5oTyDYULpx74wkfCWbs/tKyhsElwNYC/ab9wNVOOSx97st6rxFrkdQu62I9J4Lwe2Ka32NuBqgWEPvFlsAPiVrnTiM8OGn8aCw2Z3cqDtuNEHYVL1KUiJJ65U1uU17EvhxuponJ+S0xjziYanS45aO0a+8bp25a/sJNeJJxiQooQ037q3+CMZCMimiE/FJJd8nDLx1mnrn9Jd7MlISFhn9ECHAUqSZvCMgQlH7Dy8Bs+18VWnWuIjzKGtIb/jDFnJwsMLLPz/wju+crD4LyGQ/u+27qNM2gkQeoxl7AnQIlAcNTvglKuYlrApU8xK/+coBKSgtZRRhBfh5hJSSwoKat79ucdGRZpgHeCOhgIT4Tw3JZXd9Po X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Nov 2026 23:39:55.1744 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 69d1c63b-c4ea-41d0-f4d5-08df41164165 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DSM2EPF0000000C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB9132 amdgpu and radeon pick the VFCT image for a GPU by comparing the PCI bus number recorded by the BIOS at POST with the device's bus number. When the kernel renumbers buses (e.g. pci=realloc), the runtime number no longer matches the one in VFCT. commit 11c141672045f ("drm/amdgpu: Fix VFCT bus number matching with soft filter") and its radeon counterpart worked around this by accepting an entry whenever everything but the bus number matched. That picks the wrong image when a system has two identical GPUs. Instead, have the PCI core remember the secondary bus number the firmware assigned to each bridge, and make amdgpu and radeon match the VFCT bus number against it again, using the bridge above the GPU. The value is captured once, when the bridge windows are first read, so renumbering and later rescans don't overwrite it. Patch 1 adds the cached firmware secondary bus number to struct pci_dev. Patches 2 and 3 convert amdgpu and radeon to use it and drop the soft filter. Link: https://lore.kernel.org/linux-pci/20261015124843.203905-1-mario.limonciello@amd.com/ Link: https://lore.kernel.org/amd-gfx/20261019194106.2796150-1-alexander.deucher@amd.com/ Signed-off-by: Mario Limonciello --- Changes in v7: - Reword the cover letter and the PCI patch to describe the current design: the firmware secondary bus number is cached on the bridge pci_dev when its bridge windows are first read, and amdgpu/radeon match VFCT against it. - No code changes. - Link to v6: https://patch.msgid.link/20261111-vfct-regression-v6-0-393797bbb6e3@amd.com Changes in v6: - Capture the firmware secondary bus number when reading bridge windows and ignore unconfigured values so rescans cannot replace it with runtime data (Sashiko). - No change needed in the VFCT consumers; they continue to read the cached value from the upstream bridge. - Link to v5: https://patch.msgid.link/20261110-vfct-regression-v5-0-f49fae981bf3@amd.com Changes in v5: - Record the firmware secondary bus number only on the bridge struct pci_dev, guard it with a validity bit, and keep it across rescans (Bjorn, Lijo). - Drop pci_bus::number_initial and have amdgpu/radeon read the saved bridge number when matching VFCT entries. Changes in v4: - Retain secondary bus bus number for a bridge across rescans, and the child bus is initialized from it during allocation, before registration callbacks run. (Sashiko) - Rename variable to clarify it's for bridges (Lijo) - Link to v3: https://patch.msgid.link/20261026-vfct-regression-v3-0-fe9586ed6978@amd.com Changes in v3: - Preserve the firmware bus number across bridge renumbering, capturing the secondary bus number before pci_scan_bridge_extend() clears it. - Adjust member name in all patches - Add tags - Link to v2: https://patch.msgid.link/20261020-vfct-regression-v2-0-d2394d11450a@amd.com Changes in v2: - pci_alloc_dev(NULL) remains safe. - For buses behind a reassigned bridge, the PCI core now saves the firmware secondary bus number before clearing the bridge configuration and carries it into the newly allocated bus. Devices discovered there inherit that original number. - Add changes for radeon too. - Link to v1: https://patch.msgid.link/20261019-vfct-regression-v1-0-5a63ddd378dd@amd.com --- Mario Limonciello (3): PCI: Cache bridge firmware secondary bus number drm/amdgpu: Match VFCT using initial PCI bus number drm/radeon: Match VFCT using initial PCI bus number drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 23 ++++++++++------------- drivers/gpu/drm/radeon/radeon_bios.c | 25 +++++++++++-------------- drivers/pci/probe.c | 16 ++++++++++++++-- include/linux/pci.h | 4 ++++ 4 files changed, 39 insertions(+), 29 deletions(-) --- base-commit: c03c1a14507dfaf8b856c2608f9ac216021fc222 change-id: 20261019-vfct-regression-2142fc52852a Best regards, -- Mario Limonciello