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Thu, 12 Nov 2026 02:35:22 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1794447322; bh=JRkDYlrl3ziGUdvobqOMclP0M0whEvcZbmSFJ8MdrLo=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=shGXhYfO3xMKtpLDBPTgAFQAp/5BFgsCm5liYTAT/MIGmDy2UgX59upIIhiQRQyuy k0xJ6TVQlixcI8HyCsT/wRjeGkyAdm0TqBV17DkuuQJoaTQvSAaEa0Bh828+L9VmhI hbsw5ke+4QDvfdmFJC4sRY3liVntzS25cM7PQ0sM= Date: Thu, 12 Nov 2026 03:37:44 +0200 From: Laurent Pinchart To: Guoniu Zhou Cc: Frank Li , Mauro Carvalho Chehab , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Loic Poulain , linux-media@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v4 02/11] media: imx8-isi: Extend output format mask to 7 bits Message-ID: <20261112013744.GA449716@killaraus.ideasonboard.com> References: <20260929-isi_imx952-v4-0-e69f89c7c651@oss.nxp.com> <20260929-isi_imx952-v4-2-e69f89c7c651@oss.nxp.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20260929-isi_imx952-v4-2-e69f89c7c651@oss.nxp.com> Hi Zhou, On Tue, Sep 29, 2026 at 04:52:23PM +0800, Guoniu Zhou wrote: > The ISI output format field width differs across SoC generations: > i.MX8 series (MN/MP/QM/QXP) use a 6-bit field (bits 29:24), while > from i.MX8ULP onwards (including i.MX91/93/95/952) the field is > extended to 7 bits (bits 30:24) to support RAW32 and RAW14 formats. > > Extend CHNL_IMG_CTRL_FORMAT_MASK to 7 bits unconditionally since > bit 30 is unused on older platforms. > > Signed-off-by: Guoniu Zhou > --- > Changes in v3: > - Use unconditional 7-bit mask instead of per-platform approach (Laurent) > - Drop Reviewed-by from Frank Li due to significant change > > Changes in v2: > - Add Reviewed-by tag from Frank Li > --- > drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h b/drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h > index e795f4daf3ff..c704be882705 100644 > --- a/drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h > +++ b/drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h > @@ -39,7 +39,7 @@ > /* Channel Image Control Register */ > #define CHNL_IMG_CTRL 0x0004 > #define CHNL_IMG_CTRL_FORMAT(n) ((n) << 24) > -#define CHNL_IMG_CTRL_FORMAT_MASK GENMASK(29, 24) > +#define CHNL_IMG_CTRL_FORMAT_MASK GENMASK(30, 24) I've double-checked that bit 30 is reserved on all SoC versions that use a 6-bit format. Reviewed-by: Laurent Pinchart > #define CHNL_IMG_CTRL_FORMAT_RGBA8888 0x00 > #define CHNL_IMG_CTRL_FORMAT_ABGR8888 0x01 > #define CHNL_IMG_CTRL_FORMAT_ARGB8888 0x02 -- Regards, Laurent Pinchart