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Each instance wraps one of the two USB3 Type-A DRD controllers of the SoC. The register range of an instance is its window in the USB30 Type-A DRD RCSU block at 0x091c0000, from the AXI cache attribute strap register of the instance up to and including its AXI clock status register. The strap registers of the two controllers and of their PHYs are interleaved in that block, so the ranges of the two instances overlap. The Cadence USBSSP core is described by a child node at its own address. Mode strap controls are programmed through the Sky1 S5 system controller referenced by the cix,usb-syscon phandle. Signed-off-by: Hongliang Yang --- Changes in v8: - Fix the example: the USB3 PHY is a single provider shared by both controllers, so the core node references one phandle. The example still carried the per-lane two-PHY form that v5 of the PHY series used. Keep the USB2 PHY reference and describe it as usb-nop-xceiv, since it needs no configuration. - Add the vendor prefix to the two board properties: cix,ssp-disable and cix,u3-port-disable. Changes in v7: - Describe the RCSU registers of each controller as one address range starting at its AXI cache attribute register, instead of two 16-byte register slots, and drop the reg-names property. - Take the offset of the AXI clock status register from per-compatible driver data (0xec on Type-A, 0xf0 on Type-C), instead of two reg-names. - Dropped #syscon-cells from the S5 system controller binding: the property does not exist in the kernel, and the series no longer touches bindings/soc/cix. - Removed the arm64 dts from the series: it is a separate SoC patchset. Changes in v6: - Dropped the simple-bus RCSU container; each node is placed at the address of its glue registers and the core is a child at its own address. - Replaced the usbN aliases and the undocumented id property with the register offset and bit position arguments of cix,usb-syscon. - Converted probe error paths to dev_err_probe(). - Removed the unused over-current GPIO handling and the unused dr_base and cdnsp_pdev fields. - Fixed the 125us prescaler value: time * frequency - 1. - Made the AXI halt writes read-modify-write so the preserved and RW1C bits of XEC_AXI_CAP keep their state. Changes in v5: - Dropped the cix,sky1-usbss-rcsu syscon binding and the cix,usb-rcsu phandle; the glue registers are described in the controller node. - Added the MAINTAINERS entry for the glue driver. Changes in v4: - Split the combined PHY/USBSSP series into two independent series. - Restructured the RCSU registers as a shared syscon region with offsets (reverted in v5). - Fixed the indentation reported by checkpatch. Changes in v3: - Fixed the interrupt specifiers of the core nodes: the Sky1 GICv3 uses four cells, so every entry needs the fourth (empty) cell. Changes in v2: - Split the single binding into a PHY binding and a USBSSP binding. - clock-names: sof/axi/lpm/apb for the controller. - reset-names: core/apb instead of reset/preset. - Dropped axi_bmax_value from DT; it is a driver constant. - Added the MAINTAINERS entries. Changes in v1: initial version. --- .../bindings/usb/cix,sky1-usbssp.yaml | 163 ++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 164 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/cix,sky1-usbssp.yaml diff --git a/Documentation/devicetree/bindings/usb/cix,sky1-usbssp.yaml b/Documentation/devicetree/bindings/usb/cix,sky1-usbssp.yaml new file mode 100644 index 000000000000..994c805d30da --- /dev/null +++ b/Documentation/devicetree/bindings/usb/cix,sky1-usbssp.yaml @@ -0,0 +1,163 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/cix,sky1-usbssp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CIX Sky1 Cadence USBSSP Controller + +maintainers: + - Hongliang Yang + +description: | + The CIX Sky1 USBSSP controller is based on the Cadence USBSSP DRD + controller. Each instance wraps one of the two USB3 Type-A DRD + controllers of the SoC. + + The register range of an instance is a window in the USB30 Type-A DRD + RCSU block at 0x091c0000, starting at the AXI cache attribute strap + register of the instance and ending after its AXI clock status + register. The strap registers of the two controllers and of their PHYs + are interleaved in that block, so the ranges of the two instances + overlap. + + The Cadence USBSSP core itself is described by a child node at its own + address. Mode strap controls are programmed through the Sky1 S5 system + controller referenced by the cix,usb-syscon phandle, whose arguments + give the register offset and the bit position of the strap field. + + The USB2 PHY of the controller needs no configuration. It is described + as a usb-nop-xceiv device and referenced by the core node like any + other PHY. + +properties: + compatible: + const: cix,sky1-usbssp + + reg: + maxItems: 1 + description: + Window from the AXI cache attribute strap register of this instance + up to and including its AXI clock status register. + + ranges: true + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + clocks: + items: + - description: Start-of-frame clock + - description: AXI bus clock + - description: Low-power mode clock + - description: APB register interface clock + + clock-names: + items: + - const: sof + - const: axi + - const: lpm + - const: apb + + resets: + items: + - description: APB register reset + - description: Controller reset + + reset-names: + items: + - const: apb + - const: core + + cix,ssp-disable: + type: boolean + description: Disable SuperSpeed Plus mode of the controller. + + cix,u3-port-disable: + type: boolean + description: The board does not route the USB3 port of the controller. + + cix,usb-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Phandle to the Sky1 S5 system controller followed by the register + offset and the bit position of the USB mode strap field. + items: + - items: + - description: Phandle to the Sky1 S5 system controller + - description: Register offset of the USB mode strap field + - description: Bit position of the USB mode strap field + +required: + - compatible + - reg + - ranges + - "#address-cells" + - "#size-cells" + - clocks + - clock-names + - resets + - reset-names + - cix,usb-syscon + +patternProperties: + "^usb@[0-9a-f]+$": + $ref: cdns,usb3.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + usb@91c0314 { + compatible = "cix,sky1-usbssp"; + reg = <0x00 0x91c0314 0x00 0x100>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + + clocks = <&scmi_clk CLK_TREE_USB3A_H0_CLK_SOF>, + <&scmi_clk CLK_TREE_USB3A_0_AXI_GATE>, + <&scmi_clk CLK_TREE_USB3A_H0_CLK_LPM>, + <&scmi_clk CLK_TREE_USB3A_0_APB_GATE>; + clock-names = "sof", "axi", "lpm", "apb"; + resets = <&src SKY1_USBC_SS2_PRST_N>, + <&src SKY1_USBC_SS2_RST_N>; + reset-names = "apb", "core"; + cix,usb-syscon = <&src 0x424 8>; + + usb@91d0000 { + compatible = "cdns,usb3"; + reg = <0x00 0x91d0000 0x00 0x4000>, + <0x00 0x91d8000 0x00 0x8000>, + <0x00 0x91d4000 0x00 0x4000>; + reg-names = "otg", "xhci", "dev"; + dr_mode = "otg"; + + interrupts = , + , + , + ; + interrupt-names = "host", "peripheral", "otg", "wakeup"; + maximum-speed = "super-speed-plus"; + + phys = <&usb3_phy4>, <&usb2_phy4>; + phy-names = "cdns3,usb3-phy", "cdns3,usb2-phy"; + }; + }; + + usb2_phy4: usb-phy { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 93abbb315065..5144d02fc998 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2903,6 +2903,7 @@ S: Maintained T: git https://github.com/cixtech/linux-mainline.git F: Documentation/devicetree/bindings/arm/cix.yaml F: Documentation/devicetree/bindings/mailbox/cix,sky1-mbox.yaml +F: Documentation/devicetree/bindings/usb/cix,sky1-usbssp.yaml F: arch/arm64/boot/dts/cix/ F: drivers/mailbox/cix-mailbox.c K: \bcix\b -- 2.54.0