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To accommodate hardware designs, the enable and disable operations handle a 'write_en' flag, which asserts an adjacent write-enable bit (bit_idx + 1) simultaneously when modifying the gate bit. Signed-off-by: Cheng-Yu Lee Co-developed-by: Yu-Chun Lin Signed-off-by: Yu-Chun Lin --- Changes in v16: - Remove Brian's reviewed-by tag. - Replace 'CLK_HW_INIT' with 'CLK_HW_INIT_HW' and 'CLK_HW_INIT_FW_NAME' macros to avoid relying on unstable internal CCF global names. - Drop all unused NO_PARENT macro and 'rtk_clk_regmap_gate_ro_ops'. --- drivers/clk/realtek/Makefile | 1 + drivers/clk/realtek/clk-regmap-gate.c | 59 +++++++++++++++++++++++++++ drivers/clk/realtek/clk-regmap-gate.h | 54 ++++++++++++++++++++++++ 3 files changed, 114 insertions(+) create mode 100644 drivers/clk/realtek/clk-regmap-gate.c create mode 100644 drivers/clk/realtek/clk-regmap-gate.h diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile index 6fbe6e07b760..9397d677f52d 100644 --- a/drivers/clk/realtek/Makefile +++ b/drivers/clk/realtek/Makefile @@ -2,5 +2,6 @@ obj-$(CONFIG_RTK_CLK_COMMON) += clk-rtk.o clk-rtk-y += clk-rtk-common.o +clk-rtk-y += clk-regmap-gate.o clk-rtk-y += clk-regmap-pll.o clk-rtk-y += freq_table.o diff --git a/drivers/clk/realtek/clk-regmap-gate.c b/drivers/clk/realtek/clk-regmap-gate.c new file mode 100644 index 000000000000..12539e11647c --- /dev/null +++ b/drivers/clk/realtek/clk-regmap-gate.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2017-2026 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee + */ + +#include +#include +#include +#include +#include "clk-regmap-gate.h" + +static int rtk_clk_regmap_gate_update(struct clk_hw *hw, bool enable) +{ + struct rtk_clk_regmap_gate *clkg = to_rtk_clk_regmap_gate(hw); + unsigned int mask = BIT(clkg->bit_idx); + unsigned int val = enable ? mask : 0; + + /* + * Hardware specific design: to modify the gate bit, the adjacent + * write-enable bit (bit_idx + 1) must be asserted simultaneously. + */ + if (clkg->write_en) { + mask |= BIT(clkg->bit_idx + 1); + val |= BIT(clkg->bit_idx + 1); + } + + return regmap_update_bits(clkg->clkr.regmap, clkg->gate_ofs, mask, val); +} + +static int rtk_clk_regmap_gate_enable(struct clk_hw *hw) +{ + return rtk_clk_regmap_gate_update(hw, true); +} + +static void rtk_clk_regmap_gate_disable(struct clk_hw *hw) +{ + rtk_clk_regmap_gate_update(hw, false); +} + +static int rtk_clk_regmap_gate_is_enabled(struct clk_hw *hw) +{ + struct rtk_clk_regmap_gate *clkg = to_rtk_clk_regmap_gate(hw); + int ret; + u32 val; + + ret = regmap_read(clkg->clkr.regmap, clkg->gate_ofs, &val); + if (ret < 0) + return ret; + + return !!(val & BIT(clkg->bit_idx)); +} + +const struct clk_ops rtk_clk_regmap_gate_ops = { + .enable = rtk_clk_regmap_gate_enable, + .disable = rtk_clk_regmap_gate_disable, + .is_enabled = rtk_clk_regmap_gate_is_enabled, +}; +EXPORT_SYMBOL_NS_GPL(rtk_clk_regmap_gate_ops, "CLK_REALTEK"); diff --git a/drivers/clk/realtek/clk-regmap-gate.h b/drivers/clk/realtek/clk-regmap-gate.h new file mode 100644 index 000000000000..4540e73ca72b --- /dev/null +++ b/drivers/clk/realtek/clk-regmap-gate.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2017-2026 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee + */ + +#ifndef __CLK_REALTEK_CLK_REGMAP_GATE_H +#define __CLK_REALTEK_CLK_REGMAP_GATE_H + +#include "clk-rtk-common.h" + +struct rtk_clk_regmap_gate { + struct rtk_clk_regmap clkr; + unsigned int gate_ofs; + u8 bit_idx; + u32 write_en : 1; +}; + +#define __rtk_clk_regmap_gate_hw(_p) __rtk_clk_regmap_hw(&(_p)->clkr) + +#define __RTK_CLK_REGMAP_GATE_HW(_name, _parent, _ops, _flags, _ofs, _bit_idx, _write_en) \ +struct rtk_clk_regmap_gate _name = { \ + .clkr.hw.init = CLK_HW_INIT_HW(#_name, _parent, _ops, _flags), \ + .gate_ofs = _ofs, \ + .bit_idx = _bit_idx, \ + .write_en = _write_en, \ +} + +#define RTK_CLK_REGMAP_GATE_HW(_name, _parent, _flags, _ofs, _bit_idx, _write_en) \ + __RTK_CLK_REGMAP_GATE_HW(_name, _parent, &rtk_clk_regmap_gate_ops, _flags, \ + _ofs, _bit_idx, _write_en) + +#define __RTK_CLK_REGMAP_GATE_FW_NAME(_name, _parent, _ops, _flags, _ofs, _bit_idx, _write_en) \ +struct rtk_clk_regmap_gate _name = { \ + .clkr.hw.init = CLK_HW_INIT_FW_NAME(#_name, _parent, _ops, _flags), \ + .gate_ofs = _ofs, \ + .bit_idx = _bit_idx, \ + .write_en = _write_en, \ +} + +#define RTK_CLK_REGMAP_GATE_FW_NAME(_name, _parent, _flags, _ofs, _bit_idx, _write_en) \ + __RTK_CLK_REGMAP_GATE_FW_NAME(_name, _parent, &rtk_clk_regmap_gate_ops, _flags, \ + _ofs, _bit_idx, _write_en) + +static inline struct rtk_clk_regmap_gate *to_rtk_clk_regmap_gate(struct clk_hw *hw) +{ + struct rtk_clk_regmap *clkr = to_rtk_clk_regmap(hw); + + return container_of(clkr, struct rtk_clk_regmap_gate, clkr); +} + +extern const struct clk_ops rtk_clk_regmap_gate_ops; + +#endif /* __CLK_REALTEK_CLK_REGMAP_GATE_H */ -- 2.43.0