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Thu, 12 Nov 2026 02:21:35 -0500 (EST) From: Jiaxing Hu To: finley.xiao@rock-chips.com, tomeu@tomeuvizoso.net, heiko@sntech.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, ulfh@kernel.org, p.zabel@pengutronix.de, ogabbay@kernel.org, zhangqing@rock-chips.com Cc: royalnet026@gmail.com, abel.vesa@oss.qualcomm.com, sebastian.reichel@collabora.com, sidong.yang@furiosa.ai, u.kleine-koenig@baylibre.com, chaoyi.chen@rock-chips.com, diederik@cknow-tech.com, alchark@flipper.net, leonard@lausen.nl, jeff.hugo@oss.qualcomm.com, rfoss@kernel.org, shawn.lin@rock-chips.com, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, iommu@lists.linux.dev, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jiaxing Hu Subject: Re: [PATCH v16 10/16] pmdomain: rockchip: cycle an optional power-domain reset on power-on Date: Thu, 12 Nov 2026 20:21:31 +1300 Message-ID: <20261112072131.41144-1-gahing@gahingwoo.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: <20261108065917.135194-1-gahing@gahingwoo.com> <20261108065917.135194-11-gahing@gahingwoo.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi Finley, Thanks for the feedback. I agree with all three points. Some background on where the reset came from: we added it in June while debugging the IOMMU, but found the same day that it did not actually help. The real problem turned out to be that the IOMMU was missing the CBUF clocks, which is what later went into mainline as 841363ebb508. We had in fact already removed the reset in a debug patch at the time, but when the series was put together later that step was missed and did not go out with it. I went back over the commit message, and both claims in it, that the first access hangs and that the vendor kernel also cycles this reset, are not accurate. There was no actual test showing a hang on the first access, and I have checked that the vendor kernel has no such reset at all. I also retested on the current code: without the reset, with the power domain clocks back to two, and with no delay on NPU0/NPU1, both a warm reboot and a cold power-on are fine, 30 runs each. The VOP delay makes no visible difference on this board, so I will add it as you suggest. Thanks again, these were worth sorting out properly. Jiaxing