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Wed, 11 Nov 2026 23:29:55 -0800 (PST) Received: from dev.Default ([86.127.229.203]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4ba0951bf2asm81897575e9.4.2026.11.11.23.29.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Nov 2026 23:29:54 -0800 (PST) From: Agustin Santiago Isasmendi To: Russell King Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Arnd Bergmann , =?UTF-8?q?Stefan=20D=C3=B6singer?= , Navid Ghahremani , Krzysztof Kozlowski , Rob Herring , Conor Dooley , devicetree@vger.kernel.org Subject: [PATCH v2 0/2] ARM: l2c: honour status = "disabled" on the L2 cache node Date: Thu, 12 Nov 2026 08:29:51 +0100 Message-Id: <20261112072953.989664-1-isasmendi.agus@gmail.com> X-Mailer: git-send-email 2.30.2 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi Russell, l2x0_of_init() finds the L2 cache node by compatible and never looks at its status property, so a device tree cannot keep the L2 cache off. Patch 2 makes it leave a disabled node alone; patch 1 notes in the binding that the firmware must then leave the cache disabled. The user is the ZTE ZX279128S (dual Cortex-A9, L2C-310 r3p3), where a PCIe read on one CPU deadlocks against an L2C-310 line operation by physical address or a Cache Sync on the other CPU, and the board hangs within seconds of WiFi traffic. Running with the L2 cache off avoids it, and that was suggested as the fallback for the platform when a lock-based workaround was found too invasive for generic code: https://lore.kernel.org/r/20261110153522.1620088-1-isasmendi.agus@gmail.com Whether the ZX279128S device tree disables the cache is a decision for that thread; this series only makes the property work. No in-tree L2 cache node is disabled, so existing device trees are not affected. Tested on the ZTE ZXHN H3600 (not in mainline yet, on top of Navid Ghahremani's v2 platform series): with the node disabled the cache stays off (control register 0) and the system runs normally; with it enabled the cache comes up as before. Builds without warnings with W=1 (board config and multi_v7_defconfig); checkpatch --strict and dt_binding_check are clean. Changes in v2 (after Arnd's review): - drop the clean-invalidate-disable path for a cache the firmware left enabled, and with it the "factor out the number of ways" patch: the firmware is responsible for leaving the cache off, the kernel does not touch a disabled node; - new patch 1 saying so in the binding. v1: https://lore.kernel.org/r/20261111133930.3665251-1-isasmendi.agus@gmail.com Agustin Santiago Isasmendi (2): dt-bindings: cache: l2c2x0: a disabled node is left to the firmware ARM: l2c: honour status = "disabled" on the L2 cache node Documentation/devicetree/bindings/cache/l2c2x0.yaml | 3 +++ arch/arm/mm/cache-l2x0.c | 5 +++++ 2 files changed, 8 insertions(+) base-commit: c03c1a14507dfaf8b856c2608f9ac216021fc222 -- 2.30.2