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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4bb4e267dcdsm53011905e9.11.2026.11.12.01.37.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Nov 2026 01:37:31 -0800 (PST) Date: Thu, 12 Nov 2026 09:37:29 +0000 From: David Laight To: Borislav Petkov Cc: Usama Arif , dave.hansen@linux.intel.com, dsterba@suse.com, hpa@zytor.com, linux-kernel@vger.kernel.org, mingo@redhat.com, terrelln@fb.com, tglx@kernel.org, x86@kernel.org, torvalds@linux-foundation.org, kas@kernel.org, hannes@cmpxchg.org, riel@surriel.com, shakeel.butt@linux.dev, kernel-team@meta.com Subject: Re: [PATCH v3 2/2] x86/lib: Use REP MOVSB for large memcpy() on ERMS CPUs without FSRM Message-ID: <20261112093729.065afd6c@pumpkin> In-Reply-To: <20261111234608.GAavT-QFRo6EtvoL0y@fat_crate.local> References: <20261111132214.2979125-1-usama.arif@linux.dev> <20261111132214.2979125-3-usama.arif@linux.dev> <20261111234608.GAavT-QFRo6EtvoL0y@fat_crate.local> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Wed, 11 Nov 2026 15:46:08 -0800 Borislav Petkov wrote: > On Wed, Nov 11, 2026 at 05:20:53AM -0800, Usama Arif wrote: > > diff --git a/arch/x86/lib/memcpy_64.S b/arch/x86/lib/memcpy_64.S > > index 7bb146c811029..5320862e0274e 100644 > > --- a/arch/x86/lib/memcpy_64.S > > +++ b/arch/x86/lib/memcpy_64.S > > @@ -27,15 +27,13 @@ > > * > > * The 'rep movsb' itself is small enough to replace the call, but the > > * two register moves blow up the code. And one of them is "needed" > > - * only for the return value that is the same as the source input, > > + * only for the return value that is the same as the destination input, > > * which the compiler could/should do much better anyway. > > */ > > SYM_TYPED_FUNC_START(__memcpy) > > - ALTERNATIVE "jmp memcpy_orig", "", X86_FEATURE_FSRM > > - > > movq %rdi, %rax > > movq %rdx, %rcx > > - rep movsb > > + ALTERNATIVE "jmp memcpy_orig", "rep movsb", X86_FEATURE_FSRM > > RET > > SYM_FUNC_END(__memcpy) > > EXPORT_SYMBOL(__memcpy) > > @@ -45,12 +43,16 @@ SYM_PIC_ALIAS(memcpy) > > EXPORT_SYMBOL(memcpy) > > > > SYM_FUNC_START_LOCAL(memcpy_orig) > > - movq %rdi, %rax > > - movq %rdx, %rcx > > - > > cmpq $0x20, %rcx > > jb .Lhandle_tail > > > > + /* > > + * RCX holds the count for REP MOVSB and scalar copying; RDX is scratch. > > + * Shift RDX to check length >= 2048 without destroying the REP count. > > + * The 10-byte alternative fits a NOP without ERMS. > > + */ > > + ALTERNATIVE "", __stringify(shrq $11, %rdx; jnz .Lerms), X86_FEATURE_ERMS > > Sorry, this is adding more JMPs in "conditional" alternatives code and thus > turns this into a bigger and unmaintainable mess than it already is. > > The 2K limit looks like something conjured out of a thin air as it seems it > work for your particular case. I'm sure we will have to whack it in the future > because someone else will complain of the opposite. > > This needs to be done with alternative_call*, even at the price of some > duplicated code but without turning what already is a mess, into a bigger one. Multiple functions seems like a good idea. In some cases you can patch the constant in the instruction. That is safe here even if a multi-byte constant crosses a cache line because it is only an optimisation. Patching the call sites would certainly be cleaner. More interesting would be having a function with a non-standard calling convention (%rdi, %rsi, %rcx, everything else preserved, void result) so that the 5 byte call can be patched with "rep movsb; nop3". I can't see anywhere that uses the result. Maybe start with "rep movsb; nop3" and patch with the call? You'd still need a normal memcpy() for the calls gcc makes and if the address is taken. A special function to do the patching would also make sense. All Intel non-atom cpu since sandy bridge run 'rep movsb' as fast as 'rep movsq' - so you only need to worry about short copies. Whereas some of the older Zen cpu run misaligned copies slowly. So you could pick/patch the most appropriate code using more complex logic than just whether one of the X86_FEATURE_xxx bits is set. The same calling convention might make sense for memmove(). Although it probably wants a scratch register for the (dst - src < len) check (it might want dst in the scratch register!). David > > Or a static key or even with stop_machine_nmi() (currently in review) which > patches the kernel even later, when it is convenient to do so. > > Whatever it takes to keep this code readable and sane. > > But not this. > > Sorry. >