Re: [PATCH 1/1] phy: freescale: fsl-samsung-hdmi: initialize default rate

[Francesco Dolcini <francesco@dolcini.it>]

+regressions list and Emanuele

Hi,

On Wed, Nov 11, 2026 at 08:11:39AM +0100, Alexander Stein wrote:
> Am Donnerstag, 3. September 2026, 07:47:58 Mitteleuropäische Normalzeit schrieb Aristo Chen:
> > The HDMI PHY clock reports 74.25 MHz when cur_cfg is unset, but does
> > not establish that rate in hardware. The common clock framework caches
> > the reported rate when registering the clock and skips a first
> > clk_set_rate(74250000) request because the rate appears unchanged.
> > 
> > Consequently, a display whose initial mode uses a 74.25 MHz pixel clock
> > can leave the PHY with its bootloader register state and receive no
> > TMDS signal. Requesting another rate first avoids the issue because the
> > set_rate callback configures the PHY.
> > 
> > Program the 74.25 MHz table entry with the reference clock enabled
> > before registering the clock provider. recalc_rate can then report the
> > configured rate, and a skipped first rate change is safe. Also enable
> > the reference clock when restoring that configuration on resume.
> > 
> > Fixes: 6ad082bee902 ("phy: freescale: add Samsung HDMI PHY")
> > Signed-off-by: Aristo Chen <aristo.chen@canonical.com>
> 
> Unfortunately this breaks my platform (imx8mp-tqma8mpql-mba8mpxl.dts).
> With this patch applied I get the following errors in kernel log:
> > fsl-samsung-hdmi-phy 32fdff00.phy: PLL failed to lock
> > fsl-samsung-hdmi-phy 32fdff00.phy: error -ETIMEDOUT: failed to configure default rate
> > fsl-samsung-hdmi-phy 32fdff00.phy: probe with driver fsl-samsung-hdmi-phy failed with error -110
> 
> Reverting fixes my platform and HDMI as expected.

Same here on v7.4-rc2, on all the Toradex i.MX8M Plus boards in our CI
(Verdin iMX8M Plus on Dahlia, SMARC iMX8M Plus), with the very same
three errors.

#regzbot ^introduced: c01ccf91b257
#regzbot title: phy: fsl-samsung-hdmi: i.MX8MP HDMI PHY probe fails with "PLL failed to lock"

Francesco