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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-498367ba82csm16541261f8f.50.2026.11.12.04.02.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Nov 2026 04:02:51 -0800 (PST) Date: Thu, 12 Nov 2026 12:02:48 +0000 From: David Laight To: Yunhui Cui Cc: pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, dennis@kernel.org, tj@kernel.org, cl@gentwo.org, oleg@redhat.com, ast@kernel.org, daniel@iogearbox.net, andrii@kernel.org, eddyz87@gmail.com, memxor@gmail.com, martin.lau@linux.dev, song@kernel.org, yonghong.song@linux.dev, jolsa@kernel.org, emil@etsalapatis.com, ihor.solodrai@linux.dev, bjorn@kernel.org, pulehui@huawei.com, puranjay@kernel.org, broonie@kernel.org, dave@stgolabs.net, jszhang@kernel.org, tglx@kernel.org, conor.dooley@microchip.com, thuth@redhat.com, ajones@ventanamicro.com, ben.dooks@codethink.co.uk, rkrcmar@ventanamicro.com, samuel.holland@sifive.com, zong.li@sifive.com, debug@rivosinc.com, seanwascoding@gmail.com, andybnac@gmail.com, menglong8.dong@gmail.com, cyrilbur@tenstorrent.com, wangruikang@iscas.ac.cn, atishp@rivosinc.com, apatel@ventanamicro.com, arnd@arndb.de, nathan@kernel.org, nick.desaulniers+lkml@gmail.com, morbo@google.com, justinstitt@google.com, qingfang.deng@siflower.com.cn, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, bpf@vger.kernel.org, linux-arch@vger.kernel.org, llvm@lists.linux.dev Subject: Re: [PATCH v10 2/9] riscv: add infrastructure for preemptible this_cpu operations Message-ID: <20261112120248.5c8265e2@pumpkin> In-Reply-To: <20261112104149.38589-3-cuiyunhui@bytedance.com> References: <20261112104149.38589-1-cuiyunhui@bytedance.com> <20261112104149.38589-3-cuiyunhui@bytedance.com> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Thu, 12 Nov 2026 18:41:42 +0800 Yunhui Cui wrote: > +/* > + * Mark a region where the per-CPU offset and address registers may need to > + * be rewritten by exception return after migration. The three registers > + * must remain distinct for the whole region. > + */ > +#define __PCPU_GPRS_BEGIN \ > + __DEFINE_ASM_GPR_NUMS \ > + __PCPU_GPRS_ASSERT_DISTINCT \ > + "li %[off], " __PCPU_GPRS_VALUE "\n" \ > + "sh %[off], %[gprs]\n" \ > + REG_L " %[off], %[pcpu_offset]\n" \ > + "add %[addr], %[pcp], %[off]\n" > + > +#define __PCPU_GPRS_END \ > + "sh zero, %[gprs]\n" Those are quite nasty with all the hidden variable names. It wouldn't do any harm to pass the names though. David