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Miller" , Eric Dumazet , "Jakub Kicinski" , Paolo Abeni , Satha Rao , kmahammadraf Subject: [PATCH net v2] octeontx2-af: fix TX scheduler queue index width for CN20K Date: Thu, 12 Nov 2026 12:19:07 +0000 Message-ID: <20261112121907.2576520-1-kmahammadraf@marvell.com> X-Mailer: git-send-email 2.25.1 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Authority-Analysis: v=2.4 cv=GsDXaU1C c=1 sm=1 tr=0 ts=6af5aebf cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=zJRp6_cAMcgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=EAYMVhzMl8SCOHhVQcBL:22 a=VwQbUJbxAAAA:8 a=M5GUcnROAAAA:8 a=TqQ25hKhOvP58c2vajwA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMTEyMDA0OCBTYWx0ZWRfX4rL2ORBkAnAh 5OymMkQDkep/Eto/5kLzM83SbvevICaa/l5JzasHY0NfpoVV2NCjuWPtcUAU9PxXX6zjwE77Z3/ N8ArGc+JYEyFD7o2z+EzPJg08ACaiGw= X-Proofpoint-GUID: HqYVf-V2T1O2mvTIoaoTSxP5Pb-xIN4q X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTEyMDA0OCBTYWx0ZWRfX2f+z0BpjVEv6 z5Eo4yoZJqjfsRkhUN3LY7EOh/1Cxn4YDreZIancepa9wIhoJK389a6D4NTlTMx0CPr/6H0HG2U mz3CpJ4jc8ooz+0+muaQ2wIlkxwEBXDUFl72l+K3iv8s7I74Lrse41eM2tu1CcZo3aVnvqfvrML YJ+FOhHigVUry069YeeBci0h8M4rw3hK+P+TCtIqaScKBjTj18CZpa4cOS2AEOSpbLwBc3o1PZs G7iHt8JICohNK/mpuxaVM5frI52kGz3sc123UCoszw4m86AeyzycKnYGIJRqWzXeAmLLzIHafUt xqmMDX6Dt/ChLdh6lSEX2GjnGdnvDvXgzjLyhMW6EQQYP75E0RHq4fkV4enpqt2atpc2lrz+oD0 Gs0CrsyO2uJqatmsgGsixVNzlV0jNiaChlkvg34YB1EkCsQ//CAaV0Jy13BCC3oTAaiN/96G/9m LS5u9ZnxKPMZHqxlMGg== X-Proofpoint-ORIG-GUID: HqYVf-V2T1O2mvTIoaoTSxP5Pb-xIN4q X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-12_01,2026-11-11_03,2025-10-01_01 From: Satha Rao CN20K supports up to 2K TX scheduler queues per layer, so scheduler queue index handling must use 11 bits. Update TX scheduler queue index handling in both register-address decoding and hierarchy parent validation paths. Also widen TX scheduler register masking used by mailbox/config register access. Without this, queue IDs above 1023 can be truncated on CN20K, which can cause invalid hierarchy validation and incorrect TX scheduler register access for higher queue indices. Fixes: b279bbb3314e ("octeontx2-af: NIX Tx scheduler queue config support") Fixes: d06411632e80 ("octeontx2-af: enable tx shaping feature for 96xx C0") Signed-off-by: kmahammadraf Signed-off-by: Satha Rao --- v2: https://lore.kernel.org/netdev/179264357442.3290.13030103983603784553@kernel.org/ - Fix parent scheduler index decoding in hierarchy validation for CN20K. - Add Fixes tags for the affected TX scheduler index/mask paths. - Correct commit subject formatting (remove nested "Subject: [PATCH]" text). --- drivers/net/ethernet/marvell/octeontx2/af/mbox.h | 2 +- drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h index cece197d1074..1b62f9d7f00a 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h @@ -1164,7 +1164,7 @@ struct nix_txschq_config { u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */ u8 read; #define TXSCHQ_IDX_SHIFT 16 -#define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1) +#define TXSCHQ_IDX_MASK (BIT_ULL(11) - 1) #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK) u8 num_regs; #define MAX_REGS_PER_MBOX_MSG 20 diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c index 29559db68929..72d13d34829d 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c @@ -2755,7 +2755,7 @@ static bool is_txschq_hierarchy_valid(struct rvu *rvu, u16 pcifunc, int blkaddr, if (!is_valid_txschq(rvu, blkaddr, lvl, pcifunc, schq)) return false; - parent = (regval >> 16) & 0x1FF; + parent = (regval >> 16) & (is_cn20k(rvu->pdev) ? 0x7FF : 0x1FF); /* Validate MDQ's TL4 parent */ if (regbase == NIX_AF_MDQX_PARENT(0) && !is_valid_txschq(rvu, blkaddr, NIX_TXSCH_LVL_TL4, pcifunc, parent)) @@ -2849,9 +2849,9 @@ static void nix_tl1_default_cfg(struct rvu *rvu, struct nix_hw *nix_hw, } /* Register offset - [15:0] - * Scheduler Queue number - [25:16] + * Scheduler Queue number - [26:16] */ -#define NIX_TX_SCHQ_MASK GENMASK_ULL(25, 0) +#define NIX_TX_SCHQ_MASK GENMASK_ULL(26, 0) static int nix_txschq_cfg_read(struct rvu *rvu, struct nix_hw *nix_hw, int blkaddr, struct nix_txschq_config *req, -- 2.25.1