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Thu, 12 Nov 2026 10:45:47 -0800 (PST) Received: from eldorado ([2600:8802:b00:1f88::287]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-37956bad134sm369524eec.27.2026.11.12.10.45.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Nov 2026 10:45:46 -0800 (PST) From: Florian Fainelli To: linux-mips@vger.kernel.org Cc: Florian Fainelli , Thomas Bogendoerfer , Paul Burton , Paul Cercueil , Stephen Boyd , Brian Masney , Jerome Brunet , =?UTF-8?q?=E5=91=A8=E7=90=B0=E6=9D=B0=20=28Zhou=20Yanjie=29?= , Jiaxun Yang , linux-kernel@vger.kernel.org (open list), linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), hns@goldelico.com, paul@boddie.org.uk Subject: [PATCH v4 0/3] MIPS: CI20: Enable SMP with two CPUs Date: Thu, 12 Nov 2026 10:44:38 -0800 Message-ID: <20261112184441.3724150-1-f.fainelli@gmail.com> X-Mailer: git-send-email 2.53.0 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch series resurrects SMP support for the CI20 board. This was submitted back in 2020 by Zhou Yanjie. Changes in v4: • Enable the secondary CPU clock outside the raw spinlock • Mark enumerated CPUs present and assign hardware core IDs • Skip generic IPI allocation when the platform supplies both IPI callbacks • Fix generic 64-bit builds using CKSEG aliases and pointer-sized assembly macros • Reject unsupported CPU offlining with -EOPNOTSUPP • Restrict the XBurst SMP idle handler to multicore systems and recheck pending interrupts after flushing the cache Changes in v3: • Align the second line of the readl_poll_timeout_atomic() per Brian's feedback • Collected Paul's R-b and T-b tags Changes in v2: • Moved SMP sources to arch/mips/ingenic/ and the header to arch/mips/include/asm/ • Removed CONFIG_MIPS_INGENIC_SMP, using CONFIG_MACH_JZ4780 and CONFIG_SMP directly • Renamed JZ4780-specific SMP symbols to XBurst names • Changed CPU enumeration to assign consecutive logical IDs and removed the explicit two-core limit • Changed mailbox IRQ allocation failure from panic to logging and returning • Shortened commit descriptions, removed Codex attribution, and adjusted source credits and sign-offs • Kept the clock polling patch and CI20 defconfig changes unchanged, added Paul's R-b for patch #1 • Updated the kernel baseline to include additional upstream fixes Florian Fainelli (1): clk: ingenic: Poll JZ4780 CPU1 power status atomically 周琰杰 (Zhou Yanjie) (2): MIPS: Ingenic: Add XBurst SMP support MIPS: CI20: Enable SMP with two CPUs MAINTAINERS | 3 +- arch/mips/Kbuild | 1 + arch/mips/configs/ci20_defconfig | 2 + arch/mips/generic/init.c | 3 + arch/mips/include/asm/ingenic-smp.h | 20 ++ arch/mips/ingenic/Kconfig | 2 + arch/mips/ingenic/Makefile | 5 + arch/mips/ingenic/ingenic-smp-entry.S | 54 ++++++ arch/mips/ingenic/ingenic-smp.c | 262 ++++++++++++++++++++++++++ arch/mips/kernel/idle.c | 30 ++- arch/mips/kernel/smp.c | 5 +- drivers/clk/ingenic/jz4780-cgu.c | 4 +- 12 files changed, 386 insertions(+), 5 deletions(-) create mode 100644 arch/mips/include/asm/ingenic-smp.h create mode 100644 arch/mips/ingenic/Makefile create mode 100644 arch/mips/ingenic/ingenic-smp-entry.S create mode 100644 arch/mips/ingenic/ingenic-smp.c -- 2.53.0