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Thu, 12 Nov 2026 11:09:26 -0800 (PST) Received: from eldorado ([2600:8802:b00:1f88::287]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-37956bad6casm395674eec.26.2026.11.12.11.09.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Nov 2026 11:09:25 -0800 (PST) From: Florian Fainelli To: linux-mips@vger.kernel.org Cc: Florian Fainelli , Thomas Bogendoerfer , Jonathan Corbet , Shuah Khan , Randy Dunlap , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Thomas Gleixner , linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-kernel@vger.kernel.org (open list), linux-perf-users@vger.kernel.org (open list:PERFORMANCE EVENTS SUBSYSTEM), "Maciej W. Rozycki" Subject: [PATCH 0/3] MIPS: SiByte: Add HW PMU support Date: Thu, 12 Nov 2026 11:09:13 -0800 Message-ID: <20261112190916.3725141-1-f.fainelli@gmail.com> X-Mailer: git-send-email 2.53.0 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This patch series resurrects the SiByte HW PMU support which used to be supported with oprofile but was later removed. Florian Fainelli (3): MIPS: SiByte: Wire up the CPU interrupt controller MIPS: perf: Add SB1 userspace callchain unwinding MIPS: perf: Add SB1 and SB1A performance counter support Documentation/arch/mips/index.rst | 1 + Documentation/arch/mips/sb1-pmu.rst | 162 ++++++++++ arch/mips/include/asm/mach-sibyte/irq.h | 10 + arch/mips/kernel/perf_event.c | 106 ++++++- arch/mips/kernel/perf_event_mipsxx.c | 373 +++++++++++++++++++++++- arch/mips/sibyte/bcm1480/irq.c | 7 +- arch/mips/sibyte/sb1250/irq.c | 3 + include/linux/cpuhotplug.h | 1 + 8 files changed, 647 insertions(+), 16 deletions(-) create mode 100644 Documentation/arch/mips/sb1-pmu.rst create mode 100644 arch/mips/include/asm/mach-sibyte/irq.h -- 2.53.0