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Thu, 12 Nov 2026 11:32:51 -0800 (PST) Received: from AERO17.taila7786d.ts.net ([45.95.212.224]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-37955a1c5c2sm565379eec.14.2026.11.12.11.32.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Nov 2026 11:32:51 -0800 (PST) From: Pufan Jin To: Conor Dooley , Krzysztof Kozlowski , Michal Simek , Rob Herring Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Andrew Lunn Subject: [PATCH v3 0/2] ARM: dts: zynq: Add ALINX AX7Z020B development board Date: Fri, 13 Nov 2026 03:32:43 +0800 Message-ID: <20261112193245.250149-1-cyan2254650260@gmail.com> X-Mailer: git-send-email 2.56.0 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add devicetree support for the ALINX AX7Z020B board, built around the ALINX AC7Z020 system on module with a Zynq-7000 (XC7Z020-2CLG400I) SoC. Changes in v3: - Drop the vendor website Link: tags (Krzysztof Kozlowski). - Drop the empty bootargs property (Krzysztof Kozlowski). - Rename the USB PHY node from phy0 to phy, as there is only one USB PHY on the board (Krzysztof Kozlowski). - Keep the explicit mdio node under gem0, as requested during the v1 review and reviewed by Andrew Lunn in v2. dtc W=1 flags the parent node's inherited #address-cells/#size-cells. DT schema validation reports the same Zynq-7000 diagnostics as zynq-zybo-z7. The MDIO layout was also verified on hardware. - Sort I2C child nodes by address and reorder status/reg properties. - Add Krzysztof's Acked-by to patch 1. The "alinx" vendor prefix is already queued in linux-next as commit 1f06cd374a60 ("dt-bindings: vendor-prefixes: Add ALINX vendor prefix"), so it is not part of this series. Tested on hardware before the DTS style reordering: SD boot, UART console, SD card, GbE (900+ Mbps and LED hardware offload), dual CAN, I2C, QSPI and XADC. Pufan Jin (2): dt-bindings: soc: xilinx: Add ALINX AX7Z020B board ARM: dts: zynq: Add ALINX AX7Z020B development board .../bindings/soc/xilinx/xilinx.yaml | 5 + arch/arm/boot/dts/xilinx/Makefile | 1 + .../boot/dts/xilinx/zynq-alinx-ac7z020.dtsi | 71 +++++++++ .../boot/dts/xilinx/zynq-alinx-ax7z020b.dts | 146 ++++++++++++++++++ 4 files changed, 223 insertions(+) create mode 100644 arch/arm/boot/dts/xilinx/zynq-alinx-ac7z020.dtsi create mode 100644 arch/arm/boot/dts/xilinx/zynq-alinx-ax7z020b.dts Range-diff against v2: 1: f44b8dc6e6 ! 1: ca50a01108 dt-bindings: soc: xilinx: Add ALINX AX7Z020B board @@ Commit message Document the ALINX AX7Z020B development board, built around the ALINX AC7Z020 system on module. - Link: https://www.alinx.com/ Signed-off-by: Pufan Jin + Acked-by: Krzysztof Kozlowski ## Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml ## @@ Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml: properties: 2: a985ee80d4 ! 2: 477061f136 ARM: dts: zynq: Add ALINX AX7Z020B development board @@ Commit message always accessible from the PS, so expose these channels via the driver's xlnx,channels property. - Link: https://www.alinx.com/ Signed-off-by: Pufan Jin ## arch/arm/boot/dts/xilinx/Makefile ## @@ arch/arm/boot/dts/xilinx/zynq-alinx-ac7z020.dtsi (new) + +&qspi { + bootph-all; -+ status = "okay"; + num-cs = <1>; + ++ status = "okay"; ++ + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; @@ arch/arm/boot/dts/xilinx/zynq-alinx-ac7z020.dtsi (new) + #size-cells = <1>; + + partition@0 { -+ label = "boot"; + reg = <0x00000000 0x00500000>; ++ label = "boot"; + }; + + partition@500000 { -+ label = "bootenv"; + reg = <0x00500000 0x00020000>; ++ label = "bootenv"; + }; + + partition@520000 { -+ label = "image"; + reg = <0x00520000 0x00a80000>; ++ label = "image"; + }; + + partition@fa0000 { -+ label = "spare"; + reg = <0x00fa0000 0x01060000>; ++ label = "spare"; + }; + }; + }; @@ arch/arm/boot/dts/xilinx/zynq-alinx-ax7z020b.dts (new) + }; + + chosen { -+ bootargs = ""; + stdout-path = "serial0:115200n8"; + }; + -+ usb_phy0: phy0 { ++ usb_phy0: phy { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + reset-gpios = <&gpio0 46 GPIO_ACTIVE_LOW>; @@ arch/arm/boot/dts/xilinx/zynq-alinx-ax7z020b.dts (new) +}; + +&gem0 { -+ status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + ++ status = "okay"; ++ + mdio { + #address-cells = <1>; + #size-cells = <0>; @@ arch/arm/boot/dts/xilinx/zynq-alinx-ax7z020b.dts (new) +}; + +&i2c0 { -+ status = "okay"; + clock-frequency = <100000>; + ++ status = "okay"; ++ ++ temperature-sensor@48 { ++ compatible = "national,lm75"; ++ reg = <0x48>; ++ }; ++ + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; @@ arch/arm/boot/dts/xilinx/zynq-alinx-ax7z020b.dts (new) + compatible = "dallas,ds1338"; + reg = <0x68>; + }; -+ -+ temperature-sensor@48 { -+ compatible = "national,lm75"; -+ reg = <0x48>; -+ }; +}; + +&sdhci0 { + bootph-all; -+ status = "okay"; + disable-wp; ++ ++ status = "okay"; +}; + +&uart0 { @@ arch/arm/boot/dts/xilinx/zynq-alinx-ax7z020b.dts (new) + +&uart1 { + bootph-all; ++ + status = "okay"; +}; + +&usb0 { -+ status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; ++ ++ status = "okay"; +}; -- 2.56.0