On Fri, Nov 13, 2026 at 04:57:07PM +0200, Svyatoslav Ryhel wrote:
> Tegra114 has CSI pad clock enable bits embedded into PLLD/PLLD2 registers.
> Add ids for these clocks. Additionally, move TEGRA114_CLK_CLK_MAX into
> clk-tegra114 source.
> 
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> ---
>  drivers/clk/tegra/clk-tegra114.c         | 1 +
>  include/dt-bindings/clock/tegra114-car.h | 3 ++-
>  2 files changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
> index 97f5500b13b5f..80b7f64125d92 100644
> --- a/drivers/clk/tegra/clk-tegra114.c
> +++ b/drivers/clk/tegra/clk-tegra114.c
> @@ -47,6 +47,7 @@
>  #define CPU_FINETRIM_R_FCPU_6_MASK	(0x3 << CPU_FINETRIM_R_FCPU_6_SHIFT)
>  
>  #define TEGRA114_CLK_PERIPH_BANKS	5
> +#define TEGRA114_CLK_CLK_MAX		314
>  
>  #define PLLC_BASE 0x80
>  #define PLLC_MISC2 0x88
> diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h
> index a93426f008acc..b53f5942f4bae 100644
> --- a/include/dt-bindings/clock/tegra114-car.h
> +++ b/include/dt-bindings/clock/tegra114-car.h
> @@ -341,6 +341,7 @@
>  #define TEGRA114_CLK_DSIA_MUX 309
>  #define TEGRA114_CLK_DSIB_MUX 310
>  #define TEGRA114_CLK_XUSB_SS_DIV2 311

> -#define TEGRA114_CLK_CLK_MAX 312

Good riddance.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable

> +#define TEGRA114_CLK_CSIA_PAD 312
> +#define TEGRA114_CLK_CSIB_PAD 313
>  
>  #endif	/* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */
> -- 
> 2.53.0
>