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charset="utf-8" Message-Id: <20261113-hantro-robust-v3-6-82383c722ad2@gmail.com> References: <20261113-hantro-robust-v3-0-82383c722ad2@gmail.com> In-Reply-To: <20261113-hantro-robust-v3-0-82383c722ad2@gmail.com> To: Nicolas Dufresne , Benjamin Gaignard , Philipp Zabel , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Nicolas Frattaroli , Andrzej Pietrasiewicz , Ezequiel Garcia , Hans Verkuil , Jernej Skrabec , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy Cc: linux-media@vger.kernel.org, iommu@lists.linux.dev, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Sergei Khomenkov , Tharit Tangkijwanichakul , Sascha Hauer , Arun Iyengar X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1794588032; l=2987; i=aiyengar1990@gmail.com; s=20261110; h=from:subject:message-id; bh=q6Pq46ig5sFzVhXewo4JD0YaRvjUliQqE72OFoEItyg=; b=bCV7tBrPCKFdbUpYscknizIlwUrT56Wl9krvpZSnskbprlbtyeqZRtn0SbCoHIOkl7HdMgZqb SKRHwEqYZGmCwh9i7cDGNjLtbh15HYxzVa7dJOGYwHEXgD5BAV3OIMD X-Developer-Key: i=aiyengar1990@gmail.com; a=ed25519; pk=zXpRgUTrhaFe6jLyPqbBy3ccfkj04w0g2690Wv3mg+0= X-Endpoint-Received: by B4 Relay for aiyengar1990@gmail.com/20261110 with auth_id=1480 X-Original-From: Arun Iyengar Reply-To: aiyengar1990@gmail.com Content-Transfer-Encoding: 7bit From: Arun Iyengar On a job timeout, the Rockchip VEPU1 and VEPU2 reset operations mask the interrupt and clear the encode enable and AXI control registers. On RK3588, when a VEPU121 core reads an IOVA that isn't mapped, the IOMMU reports a page fault and the core never becomes idle again: its AXI transactions stay outstanding, the IOMMU can't be stalled anymore ("Enable stall request timed out", then "Disable paging request timed out" on runtime suspend), and every later job times out as well. Pulse the optional reset lines in the encoder reset operations, after stopping the core through its registers, as the Rockchip BSP MPP driver does. The job that timed out still holds the clocks. Nothing changes for device trees without the resets. Signed-off-by: Arun Iyengar --- .../media/platform/verisilicon/rockchip_vpu_hw.c | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/media/platform/verisilicon/rockchip_vpu_hw.c b/drivers/media/platform/verisilicon/rockchip_vpu_hw.c index ce3dbea70a8d..1467ae2bed1a 100644 --- a/drivers/media/platform/verisilicon/rockchip_vpu_hw.c +++ b/drivers/media/platform/verisilicon/rockchip_vpu_hw.c @@ -7,6 +7,7 @@ */ #include +#include #include "hantro.h" #include "hantro_jpeg.h" @@ -468,6 +469,31 @@ static void rk3066_vpu_dec_reset(struct hantro_ctx *ctx) vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); } +/* + * A core stuck on the bus, e.g. after an IOMMU fault, can't be stopped + * through its registers and keeps the IOMMU from stalling. Pulse its reset + * lines, if any. + */ +static void rockchip_vpu_enc_hw_reset(struct hantro_dev *vpu) +{ + int ret; + + if (!vpu->resets) + return; + + ret = reset_control_assert(vpu->resets); + if (ret) { + dev_warn(vpu->dev, "Failed to assert resets: %d\n", ret); + return; + } + + udelay(5); + + ret = reset_control_deassert(vpu->resets); + if (ret) + dev_err(vpu->dev, "Failed to deassert resets: %d\n", ret); +} + static void rockchip_vpu1_enc_reset(struct hantro_ctx *ctx) { struct hantro_dev *vpu = ctx->dev; @@ -475,6 +501,7 @@ static void rockchip_vpu1_enc_reset(struct hantro_ctx *ctx) vepu_write(vpu, H1_REG_INTERRUPT_DIS_BIT, H1_REG_INTERRUPT); vepu_write(vpu, 0, H1_REG_ENC_CTRL); vepu_write(vpu, 0, H1_REG_AXI_CTRL); + rockchip_vpu_enc_hw_reset(vpu); /* Only the interrupt handler writes this register: enable the interrupt again. */ vepu_write(vpu, 0, H1_REG_INTERRUPT); } @@ -495,6 +522,7 @@ static void rockchip_vpu2_enc_reset(struct hantro_ctx *ctx) vepu_write(vpu, VEPU_REG_INTERRUPT_DIS_BIT, VEPU_REG_INTERRUPT); vepu_write(vpu, 0, VEPU_REG_ENCODE_START); vepu_write(vpu, 0, VEPU_REG_AXI_CTRL); + rockchip_vpu_enc_hw_reset(vpu); /* Only the interrupt handler writes this register: enable the interrupt again. */ vepu_write(vpu, 0, VEPU_REG_INTERRUPT); } -- 2.55.0