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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-37955f02ff0sm11158803eec.16.2026.11.13.19.09.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Nov 2026 19:09:25 -0800 (PST) From: Deepa Guthyappa Madivalara Date: Fri, 13 Nov 2026 19:09:22 -0800 Subject: [PATCH 1/3] dt-bindings: media: qcom,mahua-iris: Add Mahua video codec X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261113-mahua_iris_enable-v1-1-b7107e1cbcaa@oss.qualcomm.com> References: <20261113-mahua_iris_enable-v1-0-b7107e1cbcaa@oss.qualcomm.com> In-Reply-To: <20261113-mahua_iris_enable-v1-0-b7107e1cbcaa@oss.qualcomm.com> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Abel Vesa Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Deepa Guthyappa Madivalara X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1794625764; l=7265; i=deepa.madivalara@oss.qualcomm.com; s=20250814; h=from:subject:message-id; bh=ghTHXTCvd7eOk6uSjXl1tAvTuMYTkm8SazpMstLCBLo=; b=57XtPUPg+8LSdf9vmav4lku38gwgL24/w45tpdryzJQPlMvVCMjnV7JGInf8+TVuk6X3Lp55j KSYQCDzXuV2BIbej0CTAVlwn2Ajzxyf276N81PJfoGj8f8ERfrdxzPA X-Developer-Key: i=deepa.madivalara@oss.qualcomm.com; a=ed25519; pk=MOEXgyokievn+bgpHdS6Ixh/KQYyS90z2mqIbQ822FQ= X-Proofpoint-ORIG-GUID: gLylpw0vd7ese1lTNO69pX7ds3LerhVP X-Proofpoint-Spam-Info: AW1haW4tMjYxMTE0MDAxMiBTYWx0ZWRfXwWv4uVSfFE+c JV/1ApMxABDKS69RSJ1N4R6BaANW78UqFJz3KMWaocRk1A2tg01IRIKp39TGCPqcobWh6BW1XcG 2D7pj+mmKr26lNhVSELa2gJCDunWQkk= X-Authority-Analysis: v=2.4 cv=c94+0h9l c=1 sm=1 tr=0 ts=6af7d0e7 cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=wyAc8u2O2XHP32wH8dUA:9 a=QEXdDO2ut3YA:10 a=6Ab_bkdmUrQuMsNx7PHu:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTE0MDAxMiBTYWx0ZWRfX4HWp/0te/hJ5 E5+ZW7pMW6yq6BzeIwAgJxZH/jB5ct/TGD/QrDqaoi8pFysPjnQI492JkmWqyrclSggl6er+cfP ClsuZFSzlbJQ/HxQF0YnmQ4AAHD37fHPAOgHoEWzzNY6E4DZ+jsMGVcbykvGggQktx+oDf5SqEp C+/y7rBPPQ2OuBZ/ATfgeX0dR2RfWVMQng30Ezh1Ml0UEUf067QlbdcUlvf4msiZ/EKUKNgChkc fC+JWzMFWmapVCnHNPirjnMJWMe3+7A4zfdmqWqEh1e+SVJ7MKaGdRbe3nZ/P7mV+h/mhVQEXNf u8rDgf9dZ3p23lajpixfMXC41LfN9zj5xHmvg115wukAu1mD2fqwSbQ8wlzAs1b2E5afSGDKaGM 5uwrSUhbeChykmHzyjTclTztL5p0Xne8K7VsdEFcHSQEq2zsj8YXfGSIHrqHdqZcYbo+8AKP6Qw A1FKXDxkQSteaGYtY+Q== X-Proofpoint-GUID: gLylpw0vd7ese1lTNO69pX7ds3LerhVP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-14_01,2026-11-11_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 impostorscore=0 phishscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 adultscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2611040001 definitions=main-2611140012 Add a devicetree binding for the Iris3.9 video encoder and decoder block found on the Qualcomm Mahua SoC. This is a single core derivative, leveraging most of Glymur data with the clks, resets present only for vcodec0 core. Signed-off-by: Deepa Guthyappa Madivalara --- .../devicetree/bindings/media/qcom,mahua-iris.yaml | 243 +++++++++++++++++++++ 1 file changed, 243 insertions(+) diff --git a/Documentation/devicetree/bindings/media/qcom,mahua-iris.yaml b/Documentation/devicetree/bindings/media/qcom,mahua-iris.yaml new file mode 100644 index 0000000000000000000000000000000000000000..cbae6bddf7fd4b67330ce47033874f3d349e5a3d --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,mahua-iris.yaml @@ -0,0 +1,243 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,mahua-iris.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Mahua SoC Iris video encoder and decoder + +maintainers: + - Vikash Garodia + +description: + The Iris video processing unit on Qualcomm Mahua SoC is a video encode and + decode accelerator. + +properties: + compatible: + oneOf: + - items: + - const: qcom,mahua-iris + - const: qcom,glymur-iris + - const: qcom,mahua-iris + + clocks: + maxItems: 6 + + clock-names: + items: + - const: core_iface + - const: core + - const: vcodec0_core + - const: vcodec0_iface + - const: core_freerun + - const: vcodec0_core_freerun + + dma-coherent: true + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: cpu-cfg + - const: video-mem + + '#address-cells': + const: 2 + + '#size-cells': + const: 2 + + non-pixel: + type: object + description: + Context bank for VPU non-pixel buffers, including compressed and internal buffers. + properties: + iommus: + maxItems: 3 + memory-region: + maxItems: 1 + required: + - iommus + - memory-region + additionalProperties: false + + pixel: + type: object + description: + Context bank for VPU pixel buffers containing uncompressed video data. + properties: + iommus: + maxItems: 1 + required: + - iommus + additionalProperties: false + + video-firmware: + type: object + description: + Context bank for the VPU firmware processing domain. + properties: + iommus: + maxItems: 1 + required: + - iommus + additionalProperties: false + + operating-points-v2: true + opp-table: + type: object + + power-domains: + maxItems: 5 + + power-domain-names: + items: + - const: venus + - const: vcodec0 + - const: mxc + - const: mmcx + + resets: + maxItems: 4 + + reset-names: + items: + - const: core_bus + - const: vcodec0_bus + - const: core + - const: vcodec0_core + +required: + - clocks + - clock-names + - compatible + - dma-coherent + - interconnects + - interconnect-names + - non-pixel + - pixel + - power-domains + - power-domain-names + - resets + - reset-names + +allOf: + - $ref: qcom,venus-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + + video-codec@aa00000 { + compatible = "qcom,mahua-iris"; + reg = <0x0aa00000 0xf0000>; + + clocks = <&gcc_video_axi0c_clk>, + <&videocc_mvs0c_clk>, + <&videocc_mvs0_clk>, + <&gcc_video_axi0_clk>, + <&videocc_mvs0c_freerun_clk>, + <&videocc_mvs0_freerun_clk>, + + clock-names = "core_iface", + "core", + "vcodec0_core", + "vcodec0_iface", + "core_freerun", + "vcodec0_core_freerun", + + dma-coherent; + + interconnects = <&hsc_noc_master_appss_proc &config_noc_slave_venus_cfg>, + <&mmss_noc_master_video &mc_virt_slave_ebi1>; + interconnect-names = "cpu-cfg", + "video-mem"; + + interrupts = ; + + memory-region = <&video_mem>; + + operating-points-v2 = <&iris_opp_table>; + + power-domains = <&videocc_mvs0c_gdsc>, + <&videocc_mvs0_gdsc>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>, + + power-domain-names = "venus", + "vcodec0", + "mxc", + "mmcx"; + + resets = <&gcc_video_axi0c_clk_ares>, + <&gcc_video_axi0_clk_ares>, + <&videocc_mvs0c_freerun_clk_ares>, + <&videocc_mvs0_freerun_clk_ares>; + reset-names = "core_bus", + "vcodec0_bus", + "core", + "vcodec0_core"; + + #address-cells = <2>; + #size-cells = <2>; + + non-pixel { + iommus = <&apps_smmu 0x1940 0x0000>, + <&apps_smmu 0x1944 0x0000>, + <&apps_smmu 0x19e0 0x0000>; + memory-region = <&iris_resv>; + }; + + pixel { + iommus = <&apps_smmu 0x1943 0x0000>; + }; + + firmware { + iommus = <&apps_smmu 0x19e2 0x0000>; + }; + + iris_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000 360000000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_low_svs>; + }; + + opp-338000000 { + opp-hz = /bits/ 64 <338000000 507000000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_svs>; + }; + + opp-366000000 { + opp-hz = /bits/ 64 <366000000 549000000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_svs_l1>; + }; + + opp-444000000 { + opp-hz = /bits/ 64 <444000000 666000000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_nom>; + }; + + opp-533333334 { + opp-hz = /bits/ 64 <533333334 800000000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_turbo>; + }; + + opp-655000000 { + opp-hz = /bits/ 64 <655000000 982000000>; + required-opps = <&rpmhpd_opp_nom>, + <&rpmhpd_opp_turbo_l1>; + }; + }; + }; -- 2.34.1