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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-37955f02ff0sm11158803eec.16.2026.11.13.19.09.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Nov 2026 19:09:26 -0800 (PST) From: Deepa Guthyappa Madivalara Date: Fri, 13 Nov 2026 19:09:23 -0800 Subject: [PATCH 2/3] arm64: dts: qcom: mahua: add iris video codec node X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261113-mahua_iris_enable-v1-2-b7107e1cbcaa@oss.qualcomm.com> References: <20261113-mahua_iris_enable-v1-0-b7107e1cbcaa@oss.qualcomm.com> In-Reply-To: <20261113-mahua_iris_enable-v1-0-b7107e1cbcaa@oss.qualcomm.com> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Abel Vesa Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Deepa Guthyappa Madivalara X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1794625764; l=2554; i=deepa.madivalara@oss.qualcomm.com; s=20250814; h=from:subject:message-id; bh=NIhQBb10oAVEd9idm4CYEPbkBor2YqP2ym0YbzLwWeE=; b=QDCsI/X5bqUbfX8kcms02h2BT3/1Mzvp2V+vSAQiU0RuybZJjEeM16F6UTFxKdTALiYzPzjRe I5e3u/0E9JOCF9pqhPP7PpNPZuQBpCuJtevklmwBBRohvgMH10knX4B X-Developer-Key: i=deepa.madivalara@oss.qualcomm.com; a=ed25519; pk=MOEXgyokievn+bgpHdS6Ixh/KQYyS90z2mqIbQ822FQ= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTE0MDAxMiBTYWx0ZWRfX9WbeGAL/gnjw nE+fl4pCYCrL7NsEwSR1CyZqgDGtJxAPJbtJyz9MrXf/yqCJf9FBBT+wsIa+z9hPus+WUVC+M3L XZn5RRpWKX7bbJX/o4lC+um/NshVdLCNk5yBCRrX1VWkkKykjOx3izFtixGs+G+msloeaRubzZe maz/C5ELAPS0ZHUtPw1LBxU/xoPDeAgRFCVfMUbqIe4eCz8JOUoSI5BZ1/Ix4r3p38KhpQBL3PA 41F/I3HzLHZJeBLHDTHi9S7Yri9zoRs+9llAyrAamTan+NKl2rCeTOTORa52PhpAlYgX3lo/tDk lI5AXbEiP/oYEsuXrSV//FDZWBb4T8PcL9WY0mjmq0skN8GLko+CeWzR6DUeH7+J58W0tNjvwNw znCI2ITlcVsPGQKMFFaF/cvRw+Y6iGDXLxrag8M8y08mDmN7mNUCILYcnvVaXX2mKsSzzd+vK6k bA+MUQHxDBNWtqSXfVw== X-Proofpoint-Spam-Info: AW1haW4tMjYxMTE0MDAxMiBTYWx0ZWRfX0BOmpeZTE3MZ p2SvHKzV7WynQuvSWXveiiF1jMLikZdrBnLSeLbqdZjmDU/66XqtlIe/10p6HigMoTUqqW+THz0 EmL9yqpwsUuvp+SURtNwFLGpLoDVrKU= X-Proofpoint-GUID: BZKunX7Odjwp9putgQh8V9trM6P8YcJl X-Authority-Analysis: v=2.4 cv=BusIUoX5 c=1 sm=1 tr=0 ts=6af7d0e8 cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=A6Af-tnAtVRmK4LPXG4A:9 a=QEXdDO2ut3YA:10 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-ORIG-GUID: BZKunX7Odjwp9putgQh8V9trM6P8YcJl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-14_01,2026-11-11_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 adultscore=0 phishscore=0 spamscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2611040001 definitions=main-2611140012 Add the iris video codec device node for the mahua SoC, overrriding the fields clocks, power-domains, resets and opp-table reflecting single core. Signed-off-by: Deepa Guthyappa Madivalara --- arch/arm64/boot/dts/qcom/mahua.dtsi | 66 +++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/mahua.dtsi b/arch/arm64/boot/dts/qcom/mahua.dtsi index a59c5ed7b48e776841db58e124c4d66225faccf8..1d01655e7623d13c43063b74d2ab086d2308e3ea 100644 --- a/arch/arm64/boot/dts/qcom/mahua.dtsi +++ b/arch/arm64/boot/dts/qcom/mahua.dtsi @@ -400,3 +400,69 @@ &tsens5 { #qcom,sensors = <15>; }; +&iris { + compatible = "qcom,mahua-iris"; + status = "okay"; + + clocks = <&gcc GCC_VIDEO_AXI0C_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>, + <&gcc GCC_VIDEO_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0C_FREERUN_CLK>, + <&videocc VIDEO_CC_MVS0_FREERUN_CLK>; + clock-names = "core_iface", "core", "vcodec0_core", + "vcodec0_iface", "core_freerun", + "vcodec0_core_freerun"; + + power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, + <&videocc VIDEO_CC_MVS0_GDSC>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>; + power-domain-names = "venus", "vcodec0", "mxc", "mmcx"; + + resets = <&gcc GCC_VIDEO_AXI0C_CLK_ARES>, + <&gcc GCC_VIDEO_AXI0_CLK_ARES>, + <&videocc VIDEO_CC_MVS0C_FREERUN_CLK_ARES>, + <&videocc VIDEO_CC_MVS0_FREERUN_CLK_ARES>; + reset-names = "core_bus", "vcodec0_bus", "core", "vcodec0_core"; + + iris_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000 360000000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_low_svs>; + }; + + opp-338000000 { + opp-hz = /bits/ 64 <338000000 507000000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_svs>; + }; + + opp-366000000 { + opp-hz = /bits/ 64 <366000000 549000000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_svs_l1>; + }; + + opp-444000000 { + opp-hz = /bits/ 64 <444000000 666000000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_nom>; + }; + + opp-533333334 { + opp-hz = /bits/ 64 <533333334 800000000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_turbo>; + }; + + opp-655000000 { + opp-hz = /bits/ 64 <655000000 982000000>; + required-opps = <&rpmhpd_opp_nom>, + <&rpmhpd_opp_turbo_l1>; + }; + }; +}; -- 2.34.1