From: Deepa Guthyappa Madivalara <deepa.madivalara@oss.qualcomm.com>
To: Vikash Garodia <vikash.garodia@oss.qualcomm.com>,
Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>,
Abhinav Kumar <abhinav.kumar@linux.dev>,
Bryan O'Donoghue <bod@kernel.org>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Abel Vesa <abelvesa@kernel.org>
Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Deepa Guthyappa Madivalara <deepa.madivalara@oss.qualcomm.com>
Subject: [PATCH 3/3] media: iris: add mahua platform data and enable qcom,mahua-iris
Date: Fri, 13 Nov 2026 19:09:24 -0800 [thread overview]
Message-ID: <20261113-mahua_iris_enable-v1-3-b7107e1cbcaa@oss.qualcomm.com> (raw)
In-Reply-To: <20261113-mahua_iris_enable-v1-0-b7107e1cbcaa@oss.qualcomm.com>
Add qcom,mahua-iris compatible to initialize the hardware
and necessary Mahua platform data describing the needed clock
resets and powerdomain tables only for one core, vcodec0.
Most of the data is leveraged from Glymur as they are the same
Iris variant. Firmware, vpu ops, buffer sizes are the same as for
Glymur.
Signed-off-by: Deepa Guthyappa Madivalara <deepa.madivalara@oss.qualcomm.com>
---
drivers/media/platform/qcom/iris/Makefile | 1 +
.../platform/qcom/iris/iris_platform_common.h | 1 +
.../media/platform/qcom/iris/iris_platform_mahua.c | 44 ++++++++++++++++++++++
.../media/platform/qcom/iris/iris_platform_mahua.h | 14 +++++++
.../media/platform/qcom/iris/iris_platform_vpu3x.c | 34 +++++++++++++++++
drivers/media/platform/qcom/iris/iris_probe.c | 4 ++
drivers/media/platform/qcom/iris/iris_vpu3x.c | 10 +++++
7 files changed, 108 insertions(+)
diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/platform/qcom/iris/Makefile
index 48570da56aa052577e05ead12bd26df090d97454..6c187d25980eabcd1c789b132e2f0bffa62fc805 100644
--- a/drivers/media/platform/qcom/iris/Makefile
+++ b/drivers/media/platform/qcom/iris/Makefile
@@ -13,6 +13,7 @@ qcom-iris-objs += iris_buffer.o \
iris_hfi_gen2_response.o \
iris_hfi_queue.o \
iris_platform_glymur.o \
+ iris_platform_mahua.o \
iris_platform_vpu2.o \
iris_platform_vpu3x.o \
iris_power.o \
diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
index 1024a2fd75a3ae2b7e194e583b91ec5f16e2773a..817b8a9e2712e7f1e335dbb8600dc033670c5cfa 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_common.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
@@ -58,6 +58,7 @@ extern const struct iris_firmware_data iris_hfi_gen1_data;
extern const struct iris_firmware_data iris_hfi_gen2_data;
extern const struct iris_firmware_data iris_hfi_milos_data;
+extern const struct iris_platform_data mahua_data;
extern const struct iris_platform_data glymur_data;
extern const struct iris_platform_data milos_data;
extern const struct iris_platform_data qcs8300_data;
diff --git a/drivers/media/platform/qcom/iris/iris_platform_mahua.c b/drivers/media/platform/qcom/iris/iris_platform_mahua.c
new file mode 100644
index 0000000000000000000000000000000000000000..14b085426ac29cf69824d1d0da142c026266a0bb
--- /dev/null
+++ b/drivers/media/platform/qcom/iris/iris_platform_mahua.c
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "iris_core.h"
+#include "iris_platform_common.h"
+
+const struct iris_power_domain_data iris_mahua_ctrl_data = {
+ .pd_names = (const char *[]) {
+ "venus",
+ },
+ .pd_cnt = 1,
+ .clk_names = (const char *[]) {
+ "core_iface", "core_freerun", "core",
+ },
+ .clk_cnt = 3,
+};
+
+const struct iris_power_domain_data iris_mahua_vcodec_data[] = {
+ {
+ .pd_names = (const char *[]) {
+ "vcodec0",
+ },
+ .pd_cnt = 1,
+ .clk_names = (const char *[]) {
+ "vcodec0_iface", "vcodec0_core_freerun", "vcodec0_core",
+ },
+ .clk_cnt = 3,
+ },
+};
+
+const char * const iris_mahua_clk_reset_table[] = {
+ "core_bus",
+ "vcodec0_bus",
+ "core",
+ "vcodec0_core",
+};
+
+const char * const iris_mahua_opp_clk_table[] = {
+ "vcodec0_core",
+ "core",
+ NULL,
+};
diff --git a/drivers/media/platform/qcom/iris/iris_platform_mahua.h b/drivers/media/platform/qcom/iris/iris_platform_mahua.h
new file mode 100644
index 0000000000000000000000000000000000000000..fa30f33c5b03b515fa57e52a1b7413406cf5823e
--- /dev/null
+++ b/drivers/media/platform/qcom/iris/iris_platform_mahua.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef __IRIS_PLATFORM_MAHUA_H__
+#define __IRIS_PLATFORM_MAHUA_H__
+
+extern const struct iris_power_domain_data iris_mahua_ctrl_data;
+extern const struct iris_power_domain_data iris_mahua_vcodec_data[1];
+extern const char * const iris_mahua_clk_reset_table[4];
+extern const char * const iris_mahua_opp_clk_table[2];
+
+#endif /* __IRIS_PLATFORM_MAHUA_H__ */
diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c
index aa03f86d19453a2f3b314d13b7137827d6939a49..0fe485b360d2a9271392f6e5a397211ed94cf99a 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c
+++ b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c
@@ -13,6 +13,7 @@
#include "iris_vpu_common.h"
#include "iris_platform_glymur.h"
+#include "iris_platform_mahua.h"
#include "iris_platform_qcs8300.h"
#include "iris_platform_sm8550.h"
#include "iris_platform_sm8650.h"
@@ -90,6 +91,39 @@ static const struct tz_cp_config tz_cp_config_vpu3[] = {
},
};
+/*
+ * Shares most of Glymur data except, num_cores
+ */
+
+const struct iris_platform_data mahua_data = {
+ .firmware_desc_gen2 = &iris_vpu36_p4_s7_gen2_desc,
+ .vpu_ops = &iris_vpu36_ops,
+ .icc_tbl = iris_icc_info_vpu3x,
+ .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x),
+ .clk_rst_tbl = iris_mahua_clk_reset_table,
+ .clk_rst_tbl_size = ARRAY_SIZE(iris_mahua_clk_reset_table),
+ .bw_tbl_dec = iris_bw_table_dec_vpu3x,
+ .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x),
+ .ctrl_data = &iris_mahua_ctrl_data,
+ .vcodec_data = iris_mahua_vcodec_data,
+ .opp_pd_tbl = iris_opp_pd_table_vpu3x,
+ .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x),
+ .opp_clk_tbl = iris_mahua_opp_clk_table,
+ /* Upper bound of DMA address range */
+ .dma_mask = 0xffe00000 - 1,
+ .inst_iris_fmts = iris_fmts_vpu3x_dec,
+ .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec),
+ .inst_caps = &platform_inst_cap_sm8550,
+ .slice_caps = &iris_vpu2_vpu3x_slice_caps,
+ .tz_cp_config_data = iris_glymur_tz_cp_config,
+ .tz_cp_config_data_size = ARRAY_SIZE(iris_glymur_tz_cp_config),
+ .num_vpp_pipe = 4,
+ .max_session_count = 16,
+ .num_cores = 1,
+ .max_core_mbpf = NUM_MBS_8K * 2,
+ .max_core_mbps = ((7680 * 4320) / 256) * 60,
+};
+
const struct iris_platform_data glymur_data = {
.firmware_desc_gen2 = &iris_vpu36_p4_s7_gen2_desc,
.vpu_ops = &iris_vpu36_ops,
diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c
index 411ef7ef8dae957fae1ca47131e84244e3306ba6..cf2e92f440351e7b0aaf19c4c71db90d8a2deee7 100644
--- a/drivers/media/platform/qcom/iris/iris_probe.c
+++ b/drivers/media/platform/qcom/iris/iris_probe.c
@@ -550,6 +550,10 @@ static const struct dev_pm_ops iris_pm_ops = {
};
static const struct of_device_id iris_dt_match[] = {
+ {
+ .compatible = "qcom,mahua-iris",
+ .data = &mahua_data,
+ },
{
.compatible = "qcom,glymur-iris",
.data = &glymur_data,
diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c
index 375defbb959424df5a6b0033af6e267187f97333..e981c8f93318c5afd5ead162e00690a0c6054edf 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu3x.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c
@@ -365,6 +365,16 @@ static int iris_vpu36_check_core_load(struct iris_inst *inst, bool mbpf)
new_load = mbpf ? iris_get_mbpf(inst) : iris_get_mbps(inst);
select_core0 = core0_load + new_load <= max_load && core0_session_cnt < max_session_cnt;
+
+ if (platform_data->num_cores == 1) {
+ if (select_core0) {
+ inst->core_id = IRIS_VCODEC0;
+ return 0;
+ }
+
+ return -ENOMEM;
+ }
+
select_core1 = core1_load + new_load <= max_load && core1_session_cnt < max_session_cnt;
if (select_core0 && select_core1)
--
2.34.1
prev parent reply other threads:[~2026-11-14 3:09 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-14 3:09 [PATCH 0/3] media: iris: Add support for mahua platform Deepa Guthyappa Madivalara
2026-11-14 3:09 ` [PATCH 1/3] dt-bindings: media: qcom,mahua-iris: Add Mahua video codec Deepa Guthyappa Madivalara
2026-11-14 3:09 ` [PATCH 2/3] arm64: dts: qcom: mahua: add iris video codec node Deepa Guthyappa Madivalara
2026-11-14 3:09 ` Deepa Guthyappa Madivalara [this message]
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