From: "Rong Zhang" <rongrong@oss.cipunited.com>
To: "Keguang Zhang" <keguang.zhang@gmail.com>,
"Wim Van Sebroeck" <wim@linux-watchdog.org>,
"Guenter Roeck" <linux@roeck-us.net>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Thomas Bogendoerfer" <tsbogend@alpha.franken.de>
Cc: "Rong Zhang" <i@rong.moe>, "Yao Zi" <me@ziyao.cc>,
"Icenowy Zheng" <uwu@icenowy.me>,
"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
<linux-mips@vger.kernel.org>, <linux-watchdog@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
"Rong Zhang" <rongrong@oss.cipunited.com>,
"Conor Dooley" <conor@kernel.org>
Subject: [PATCH v2 4/8] MIPS: Loongson64: dts: ls7a-pch: Use hex in ranges and reg properties
Date: Fri, 13 Nov 2026 18:51:11 +0800 [thread overview]
Message-ID: <20261113-mips-ls7a-wdt-v2-4-e8abd6b2f77c@oss.cipunited.com> (raw)
In-Reply-To: <20261113-mips-ls7a-wdt-v2-0-e8abd6b2f77c@oss.cipunited.com>
The ls7a-pch.dtsi mixes two different styles of addresses and sizes.
Some use a all-hex style while some use a semi-dec-semi-hex style.
The latter style is confusing and hard to read, so convent all ranges
and reg properties into the former style.
Suggested-by: Conor Dooley <conor@kernel.org>
Link: https://msgid.link/20261111-unlucky-parrot-eb416eb0c794@spud
Signed-off-by: Rong Zhang <rongrong@oss.cipunited.com>
---
The following changes will replace ls7a_uart*'s clock-frequency
properties. There are reg properties with the unfavoured style around
the context, so I decided that this series should fix them as well as
other properties for address and size.
---
arch/mips/boot/dts/loongson/ls7a-pch.dtsi | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
index 28038b8cdd14..9f0a183bd348 100644
--- a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
+++ b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
@@ -5,14 +5,14 @@ pch: bus@10000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
- ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* PIO & CONF & APB */
- 0 0x20000000 0 0x20000000 0 0x10000000
- 0 0x40000000 0 0x40000000 0 0x40000000 /* PCI MEM */
- 0xe00 0x00000000 0xe00 0x00000000 0x100 0x0000000>;
+ ranges = < 0x0 0x10000000 0x0 0x10000000 0x0 0x10000000 /* PIO & CONF & APB */
+ 0x0 0x20000000 0x0 0x20000000 0x0 0x10000000
+ 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000 /* PCI MEM */
+ 0xe00 0x00000000 0xe00 0x00000000 0x100 0x00000000>;
pic: interrupt-controller@10000000 {
compatible = "loongson,pch-pic-1.0";
- reg = <0 0x10000000 0 0x400>;
+ reg = <0x0 0x10000000 0x0 0x400>;
interrupt-controller;
interrupt-parent = <&htvec>;
loongson,pic-base-vec = <0>;
@@ -22,7 +22,7 @@ pic: interrupt-controller@10000000 {
lpc: interrupt-controller@10002000 {
compatible = "loongson,ls7a-lpc";
- reg = <0 0x10002000 0 0x1000>;
+ reg = <0x0 0x10002000 0x0 0x1000>;
interrupt-controller;
interrupt-parent = <&pic>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
@@ -32,7 +32,7 @@ lpc: interrupt-controller@10002000 {
ls7a_uart0: serial@10080000 {
compatible = "ns16550a";
- reg = <0 0x10080000 0 0x100>;
+ reg = <0x0 0x10080000 0x0 0x100>;
clock-frequency = <50000000>;
interrupt-parent = <&pic>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
@@ -42,7 +42,7 @@ ls7a_uart0: serial@10080000 {
ls7a_uart1: serial@10080100 {
status = "disabled";
compatible = "ns16550a";
- reg = <0 0x10080100 0 0x100>;
+ reg = <0x0 0x10080100 0x0 0x100>;
clock-frequency = <50000000>;
interrupt-parent = <&pic>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
@@ -52,7 +52,7 @@ ls7a_uart1: serial@10080100 {
ls7a_uart2: serial@10080200 {
status = "disabled";
compatible = "ns16550a";
- reg = <0 0x10080200 0 0x100>;
+ reg = <0x0 0x10080200 0x0 0x100>;
clock-frequency = <50000000>;
interrupt-parent = <&pic>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
@@ -62,7 +62,7 @@ ls7a_uart2: serial@10080200 {
ls7a_uart3: serial@10080300 {
status = "disabled";
compatible = "ns16550a";
- reg = <0 0x10080300 0 0x100>;
+ reg = <0x0 0x10080300 0x0 0x100>;
clock-frequency = <50000000>;
interrupt-parent = <&pic>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
@@ -71,7 +71,7 @@ ls7a_uart3: serial@10080300 {
rtc0: rtc@100d0100 {
compatible = "loongson,ls7a-rtc";
- reg = <0 0x100d0100 0 0x78>;
+ reg = <0x0 0x100d0100 0x0 0x78>;
interrupt-parent = <&pic>;
interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
};
@@ -83,8 +83,8 @@ pci@1a000000 {
#size-cells = <2>;
msi-parent = <&msi>;
- reg = <0 0x1a000000 0 0x02000000>,
- <0xefe 0x00000000 0 0x20000000>;
+ reg = < 0x0 0x1a000000 0x0 0x02000000>,
+ <0xefe 0x00000000 0x0 0x20000000>;
ranges = <0x01000000 0x0 0x00020000 0x0 0x18020000 0x0 0x00020000>,
<0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
@@ -479,7 +479,7 @@ isa@18000000 {
compatible = "isa";
#address-cells = <2>;
#size-cells = <1>;
- ranges = <1 0 0 0x18000000 0x20000>;
+ ranges = <0x1 0x00000000 0x0 0x18000000 0x20000>;
};
};
};
--
2.55.0
next prev parent reply other threads:[~2026-11-13 10:51 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-13 10:51 [PATCH v2 0/8] watchdog: loongson1: Add Loongson-7A watchdog support Rong Zhang
2026-11-13 10:51 ` [PATCH v2 1/8] dt-bindings: watchdog: loongson,ls1x-wdt: Add compatible for Loongson-7A Rong Zhang
2026-11-13 17:17 ` Conor Dooley
2026-11-13 10:51 ` [PATCH v2 2/8] MIPS: Loongson64: env: Don't warn if UART has clocks node when fixing up FDT Rong Zhang
2026-11-13 10:51 ` [PATCH v2 3/8] MIPS: Loongson64: dts: ls7a-pch: Add missing #address-cells to interrupt controllers Rong Zhang
2026-11-13 10:51 ` Rong Zhang [this message]
2026-11-13 10:51 ` [PATCH v2 5/8] MIPS: Loongson64: dts: ls7a-pch: Add miscellaneous clock node Rong Zhang
2026-11-13 10:51 ` [PATCH v2 6/8] MIPS: Loongson64: dts: ls7a-pch: Bind UART nodes to miscellaneous clock Rong Zhang
2026-11-13 10:51 ` [PATCH v2 7/8] MIPS: Loongson64: dts: ls7a-pch: Add watchdog node Rong Zhang
2026-11-13 10:51 ` [PATCH v2 8/8] MIPS: loongson3_defconfig: Enable LOONGSON1_WDT by default Rong Zhang
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