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[64.207.253.118]) by smtp.gmail.com with ESMTPSA id 5614622812f47-56e70c58f9bsm2712225b6e.13.2026.11.13.12.35.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Nov 2026 12:35:11 -0800 (PST) From: Ryan Brue Subject: [PATCH RESEND 0/2] clk: mediatek: Fix FHCTL DDS mask widths for mt8173, mt6795 Date: Fri, 13 Nov 2026 14:34:54 -0600 Message-Id: <20261113-mt8173-fix-dds-mask-width-v1-0-c8d1e3288df9@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAAAAAAAA/42OsQ6CMBRFf6V5M8+0RQGZHGR10NEwQFvgqQXTI mII/27AH3C9OTnnTuCNI+MhZRM4M5CnroWUiYCBaoq2NkgaUgaSy4jvhUTbJyIOsaIRtfZoC3/ HN+m+wUiVsVBRZbZaQMDg6UxF4+q+wjm7ZKcj5L/dv8qbUf0iXsiGfN+5z3piECv/R28QyDHUX HG5lyrZqUNtC3psVGchn+f5Cwnp5IDcAAAA X-Change-ID: 20260912-mt8173-fix-dds-mask-width-6cb71c6fe4d1 To: Stephen Boyd , Brian Masney , Jerome Brunet , Matthias Brugger , AngeloGioacchino Del Regno , Chen-Yu Tsai Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Ryan Brue X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1794602109; l=1971; i=ryanbrue.dev@gmail.com; s=20260906; h=from:subject:message-id; bh=SOLu4jzxQrQXcZ93wAkCZjEM/VLMoV7Mr0LjnwhotLc=; b=fFa1XmGpk3uBIN1Zz6dT/QjiYTDVTbfEew2GPALp8trqTIHfGKnKk9edIoN7tUBqvwxjac2jk emNoj2NFPYmDGP15GLsBdV+AHx657qde8qsIrnkzqjM7JUqLtbxn51N X-Developer-Key: i=ryanbrue.dev@gmail.com; a=ed25519; pk=KsUvVaP//v/2q+ZBuacc7cLbsyEYn+AD71Sn28oZWKo= Discovered this while working on bringup for the Amazon Fire HD 10 (2017). In f222a1baec5f ("clk: mediatek: mt6795: Add support for frequency hopping through FHCTL"), and 45a5cbe05d1f ("clk: mediatek: mt8173: Add support for frequency hopping through FHCTL"), the DDS masks were set to the same GENMASK(21, 0) as mt8186, mt8192, and mt8195, despite not having the same pcwbits (21 as opposed to 22). These two patches correct that. Tested on an Amazon Fire HD 10 (2017), an mt8173 tablet, across 6 MMPLL rate changes. All of them timed out prior to this patchset, and all of them succeed with the patchset. mt8173 currently doesn't use FHCTL, but this will correct it for the future in case it does get used. I do not have an mt6795 to test with, but mt6795-sony-xperia-m5.dts is an actual consumer of the FHCTL node, and switches it on for mainpll, mpll and msdcpll. If someone has that device to test the second patch, that would be appreciated. I do believe this is the correct fix though regardless. Signed-off-by: Ryan Brue --- RESEND: no changes since v1 [1], rebased onto v7.4-rc2, with Angelo's Reviewed-by collected. Jerome noted these go through Angelo's MediaTek clk pull request for 7.5. The Assisted-by: LLM trailer is dropped for the new contributing guidelines. The patches were still developed with the help of an LLM. [1] https://lore.kernel.org/all/20260912-mt8173-fix-dds-mask-width-v1-0-3d0c0292c85c@gmail.com/ --- Ryan Brue (2): clk: mediatek: mt8173: fix the FHCTL DDS mask width clk: mediatek: mt6795: fix the FHCTL DDS mask width drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 2 +- drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) --- base-commit: 7475ea8b58616b33c04afb976cf0fbaad9dd63fb change-id: 20260912-mt8173-fix-dds-mask-width-6cb71c6fe4d1 Best regards, -- Ryan Brue