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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by MWH0EPF000C6191.mail.protection.outlook.com (10.167.249.106) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.615.4 via Frontend Transport; Fri, 13 Nov 2026 08:14:57 +0000 Received: from satlexmb08.amd.com (10.181.42.217) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.53; Thu, 12 Nov 2026 12:47:10 -0600 Received: from xhdsneeli40.xilinx.com (10.180.168.240) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server id 15.2.2562.53 via Frontend Transport; Thu, 12 Nov 2026 12:47:05 -0600 From: Srinivas Neeli Subject: [PATCH net-next v4 0/8] Add Xilinx TSN Endpoint Ethernet MAC driver Date: Fri, 13 Nov 2026 00:16:44 +0530 Message-ID: <20261113-patches_v2_external-v4-0-56bb26f042a4@amd.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; 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The v1 posting sent all 20 patches (wrapper, endpoint and the DSA switch) as one series. Following the review feedback to split it, this series sends only the wrapper and endpoint side (patches 1-8). The DSA switch driver, tag protocol, MDIO, phylink, PTP and bridge offloads will follow as a separate series once this base lands. IP Core Overview: The AMD LogiCORE 100M/1G TSN Subsystem IP solution (named as TSN Endpoint Ethernet MAC IP in the IP catalog) implements IEEE 802.1 Time Sensitive Networking (TSN) Standards and provides a low latency Bridged Endpoint or Endpoint only solutions. The bridged endpoint solution consists of a 3-port switch that connects to an endpoint including Linux software drivers. For Bridged Endpoint (Switch Endpoint), two ports connects to the network and one port connects to an internal Endpoint. It supports the use of GMII/RGMII interfaces connecting to a physical-side interface (PHY) chip with full duplex 100 Mb/s and 1 Gb/s operations. Features: - IP Customizable to generate TSN Endpoint or Bridged Endpoint solution - Supports interface to network software stack - Designed to comply with the following IEEE standards - 802.1AS : Precision Time Protocol (PTP) synchronization - 802.1Qav : Credit-Based Shaper for traffic shaping - 802.1Qbv : Time-Aware Shaper for scheduled traffic - 802.1Qbu : Frame Preemption for ultra-low latency - 802.1CB : Frame Replication and Elimination for redundancy - 802.1Qcc : Stream Reservation Protocol (SRP) - IP is customizable to enable various TSN feature-sets - Supports 2 to 8 priority queues for scheduled, reserved (IEEE 802.1 Qav Credit Based Shaper) and best effort traffic classes - Provides feature rich Ethernet Switch that caters to various network needs * 3-port Switch (2-external, 1-internal) * Programmable cut-through and store-forward operations * 4-port Switch (2-external, 2-internal) extension through 'Endpoint Extension' and 'Endpoint Packet Switching' features - Solution validated on ZCU102 & ZC702 AMD Evaluation boards. Sample hardware architecture diagram for Bridge End Point like below: +------------------+ | MCDMA | +---------+--------+ Q0---Q7 | +------------------------------------------------------------ + | | TSN sub system(Bridge End Point) | | | | | +------+----+ Port 0 +-----------------------+ | | | EndPoint |<--------->| TSN Switch | | | | (EP) | +----+-------------+----+ | | +-----------+ | | | | | | | | Port 1 Port 2 | | | | | | +-----------+ +-----------+ | | | MAC-1 | | MAC-2 | | | | (ETH1) | | (ETH2) | | | +-----+-----+ +-----+-----+ | | | | | | | | | +-------------------------------------------------------------+ | | RGMII RGMII | | +-----------+ +-----------+ | PHY1 | | PHY2 | | (Port 0) | | (Port 2) | +-----------+ +-----------+ The endpoint is capable of Qbv scheduling and is connected to hardware that implements time-triggered per-stream scheduling as specified in IEEE 802.1Qcc-2018 Annex U.1.3. Software Driver Overview: This series adds the wrapper and endpoint side of the IP. The switch-facing part is exposed through the Distributed Switch Architecture (DSA) framework in a follow-up series, so that MAC1 and MAC2 show up to Linux as switch ports with the endpoint acting as the CPU/conduit port. The endpoint frames are already classified by source-port id and tagged with DSA port metadata here, so the switch series can consume them without further endpoint change. Since the endpoint must be exposed to users for Qbv and time-triggered per-stream schedule configuration, it requires a user-facing netdev, which also aligns well with the DSA model. In addition, the hardware lacks a destination-port selector and does not provide an independent per-port forwarding mask. As a result, standalone port isolation is achieved using a private VLAN that contains only the selected port and the endpoint. The DSA framework enables reuse of the tag_8021q helpers to manage these VLANs, insert the destination-port VLAN tag (which is stripped by the hardware before egress on the wire), and seamlessly handle transitions between standalone and bridged operation. Wrapper driver: - Binds the top-level IP node, acquires and enables the IP-block clocks. - Spawns the endpoint (and, later, switch) blocks as child platform devices via devm_of_platform_populate() and carries no netdev or register access of its own. Endpoint driver: - Implements the conduit net_device that Linux DMA traffic flows through on its way to and from the switch fabric. - Manages multi-queue TX and RX descriptor rings using the dmaengine framework for high-performance packet transfer. - Classifies each received frame by the source-port id carried in the RX descriptor sideband metadata and attaches DSA port metadata so the DSA core can demux it to the right user port netdev. Changes in v4: - Rebase onto net-next, which now carries the AXI MCDMA dmaengine changes merged for v7.4-rc1. Commit 5b585cc87781 ("dmaengine: xilinx_dma: Move descriptors to done list based on completion bit") keeps RX buffers owned by the engine until their descriptor completes, and commit 5f677afc9567 ("dmaengine: xilinx_dma: Extend metadata handling for AXI DMA and MCDMA") provides the RX sideband metadata the endpoint reads. The series no longer has an external dependency. - binding: bound the queueN children from above as well as below, so a device tree with more queues than xlnx,num-priorities is rejected, and state that each priority queue must use a distinct TX channel. Add the optional xlnx,max-learning-entries switch property. - Kconfig: drop the reference to the companion DSA driver, which is not part of this series. - endpoint MAC: use alloc_etherdev() so the eth%d name is registered with NET_NAME_ENUM. - endpoint DMA parse: use alloc_etherdev_mqs() for the multi-queue netdev, and reject xlnx,num-priorities outside the 2..8 range the binding allows. - endpoint MCDMA bring-up: describe @dma_address as a DMA address in the kernel-doc. - endpoint RX: report the ring as armed when the refill submitted at least one descriptor, so ndo_open no longer fails when a buffer completes before the ring is tested. - endpoint TX: call skb_tx_timestamp() before dmaengine_submit(), add .get_ts_info so ethtool reports software TX timestamps, and terminate the TX channels before netif_tx_disable() in ndo_stop so a completion cannot wake a queue while the channels are freed. Extend the @closing kernel-doc to the TX completion. - Link to v3: https://patch.msgid.link/20261016-patches_v2_external-v3-0-e33d3960ca1e@amd.com Changes in v3: - cover letter: explain why the switch-facing part is implemented as DSA, what the endpoint netdev provides beyond being the conduit, and how RX demultiplexing and TX port selection map onto the hardware. - binding: rename ports to ethernet-ports and port@0..2 to ethernet-port@0..2, the preferred names for a new binding. Require reg on the CPU ethernet-port@0 and pin reg to the unit address on the external ports (literal ethernet-port@1 reg=1 and ethernet-port@2 reg=2 instead of a shared enum). Require queue0 in tx-queues-config, and add contains rules so dma-names must carry at least one tx_chan and one rx_chan. - endpoint MAC: register the netdev with the standard eth%d name (NET_NAME_UNKNOWN) instead of a custom "ep%d". - endpoint DMA parse: state the queueN to TX channel mapping in the commit body rather than only in the changelog. Rename the counting helper to ep_count_dma_channels() and the RX map to rx_dma_chan_map, keep the RX map in a probe local, and document the TSN_DMA_CH_INVALID sentinel in the tx_dma_chan_map kernel-doc. - endpoint MCDMA bring-up: acquire every TX and RX channel at probe and hold them until remove, so ndo_open only builds the rings and no deferral can reach userspace. Reset the controller through the first held channel. Move the closing flag and the circ_buf.h and spinlock.h includes to the RX patch that first uses them, and drop the unused io.h include. - endpoint RX: check the dmaengine_submit() cookie before advancing ring_head, and free the buffer if the submit fails. Use scoped_guard() rather than guard() for the rx_lock, per the netdev cleanup.h guidance. Introduce the closing flag here, alongside its first reader. - endpoint TX: free a DMA-error frame with dev_kfree_skb_any() and a completed one with dev_consume_skb_any(). Add skb_tx_timestamp() at the hardware handoff. Skip the queue wake while closing, using __netif_txq_completed_wake() with the closing flag. - endpoint RX to DSA: reword the commit message to describe the metadata this patch adds, and drop the claim that RX frames already reach the swpN netdevs. - Link to v2: https://patch.msgid.link/20260909-patches_v2_external-v2-0-3a40babaff4c@amd.com - This series has a dependency on the MCDMA patches, which are currently not present in net-next: https://lore.kernel.org/all/20260818174151.1608971-1-srinivas.neeli@amd.com Changes in v2: - Split the original 20-patch series. This v2 carries only the wrapper and endpoint (patches 1-8). The DSA switch driver, tag protocol and offloads will be posted as a separate follow-up series. - binding: describe only the Bridged Endpoint configuration, drop reg from the wrapper node (it has none of its own, ranges covers the child windows), rename ep-mac@ to ethernet@ and mdio-mac1/2 to mdio-1/2, cap the DMA channels at 8 (dma-names maxItems 16, tx_chan/rx_chan [0-7], dma-channel-num max 7), use a ports/ethernet-ports container and require port@0, port@1 and port@2, add reg (enum [1, 2]) and require reg, phy-mode and phy-handle on the external ports (gmii/rgmii/rgmii-id), and add minItems on the switch interrupts. - Kconfig: depend on OF_ADDRESS instead of OF && HAS_IOMEM, point the help text at the companion DSA driver rather than a symbol that does not exist yet, and drop the mod_devicetable.h include (platform_device.h pulls it in). - endpoint: name the netdev ep%d instead of a fixed "ep", drop the mapped but unused register window, use dev_kfree_skb_any() on the drop path, and drop the mod_devicetable.h include. - endpoint DMA: check xlnx,dma-channel-num against the channels dma-names lists, require one queue per tx_chan and num-priorities equal to the TX channel count, cap TX/RX at 8, error out on an unknown dma-names entry, and drop the unreachable count guards. - endpoint MCDMA bring-up: request a channel at probe time so -EPROBE_DEFER stays in the probe path and never reaches ndo_open, and request channels by their real dma-names index instead of a dense 0..N-1 sequence. - endpoint RX: serialise the refill against teardown under a per-channel lock, recover a drained ring with a refill timer instead of stalling, fail ndo_open if a channel cannot arm any descriptor, take the ring size from the channel, shut the refill timer down with timer_shutdown_sync() at teardown, and return true from the refill helper when it arms a descriptor. - endpoint TX: take the scatterlist count from skb_to_sgvec(), check dmaengine_submit() before advancing the ring and charging BQL, publish the ring head and tail with WRITE_ONCE(), move tx_lock into the per-channel struct so independent TX queues do not share one lock, use the spinlock_bh guard class in the completion callback, and use dmaengine_prep_slave_sg(). - endpoint RX to DSA: attach the port metadata only when the netdev is a DSA conduit, take a counted dst reference (dst_hold() + skb_dst_set()) so the dst survives the __netif_rx() backlog handoff without skb_dst_force() in softirq, and release it with dst_release() at teardown. Previous versions: v1 (full 20-patch series, now split): https://lore.kernel.org/lkml/20260807104431.157230-1-nagadheeraj.rottela@amd.com/ Test information: - Validated these changes on the net-next branch with the MCDMA metadata patches cherry-picked from linux-next, along with the series listed below https://lore.kernel.org/all/20260713072146.45269-1-srinivas.neeli@amd.com/ - The endpoint RX path depends on AXI MCDMA metadata support in the dmaengine driver. On plain net-next, xilinx_mcdma_prep_slave_sg() does not attach metadata_ops and desc_metadata_modes stays 0 for XDMA_TYPE_AXIMCDMA, so dmaengine_desc_get_metadata_ptr() returns -ENOTSUPP and ep_dma_rx_cb() would drop every received frame. The series therefore depends on the MCDMA metadata support that extends metadata_ops to XDMA_TYPE_AXIMCDMA and returns the descriptor status word (index 0 is status, index 1 is the sideband word carrying TID/TDEST/TUSER, index 2 onward is the app words). That dmaengine work is a prerequisite for RX to function and the TSN patches touch no dmaengine code. It will be posted to the dmaengine tree and this series carries a Depends-on note plus a lore link once it is on-list. - Performed ping, iperf3 and multi-queue TX/RX tests on the ZynqMP ZCU102 platform, with the endpoint conduit up and both external MACs cabled to peer NICs. Also ran teardown and probe-defer stress under KASAN and lockdep with no use-after-free or locking splats. Signed-off-by: Srinivas Neeli --- Nagadheeraj Rottela (1): net: xilinx: tsn: deliver endpoint RX frames to DSA user ports Srinivas Neeli (7): dt-bindings: net: add Xilinx TSN Endpoint Ethernet MAC net: xilinx: tsn: add TSN endpoint wrapper driver net: xilinx: tsn: add endpoint MAC driver skeleton net: xilinx: tsn: parse endpoint DMA channel configuration net: xilinx: tsn: bring up the endpoint MCDMA channels net: xilinx: tsn: add the endpoint RX data path net: xilinx: tsn: add the endpoint TX data path .../net/xlnx,tsn-endpoint-ethernet-mac.yaml | 536 ++++++++++ MAINTAINERS | 8 + drivers/net/ethernet/xilinx/Kconfig | 1 + drivers/net/ethernet/xilinx/Makefile | 1 + drivers/net/ethernet/xilinx/tsn/Kconfig | 15 + drivers/net/ethernet/xilinx/tsn/Makefile | 2 + drivers/net/ethernet/xilinx/tsn/xilinx_tsn.h | 15 + drivers/net/ethernet/xilinx/tsn/xilinx_tsn_ep.c | 1094 ++++++++++++++++++++ drivers/net/ethernet/xilinx/tsn/xilinx_tsn_main.c | 107 ++ 9 files changed, 1779 insertions(+) --- base-commit: 6584acd42820478910a771efb28a355a707e9cb0 change-id: 20260831-patches_v2_external-36421e557430 Best regards, -- Srinivas Neeli