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[174.29.1.49]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-8628817d979sm2034202a34.22.2026.11.13.00.49.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Nov 2026 00:49:17 -0800 (PST) From: James Hilliard Date: Fri, 13 Nov 2026 01:48:43 -0700 Subject: [PATCH net 4/4] net: phylink: reinitialize the PHY after an MII reset X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261113-submit-phy-mii-reset-v1-v1-4-02a55f352a91@gmail.com> References: <20261113-submit-phy-mii-reset-v1-v1-0-02a55f352a91@gmail.com> In-Reply-To: <20261113-submit-phy-mii-reset-v1-v1-0-02a55f352a91@gmail.com> To: Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Michael Chan , Hauke Mehrtens , Andrew Lunn Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, James Hilliard X-Mailer: b4 0.15.2 phylink handles SIOCSMIIREG with a raw MDIO write, bypassing the reset handling in phy_mii_ioctl(). A BMCR reset of the attached Clause 22 PHY therefore clears hardware state without running the driver initialization callbacks. The PHY worker continues using the old software state. Delegate BMCR reset writes for the attached Clause 22 PHY to phy_mii_ioctl(), which quiesces the PHY worker across reset completion and driver initialization. Select this path in the register-write helper after the Clause 45 cases, retaining raw access for the other register writes. Fixes: 9525ae83959b ("phylink: add phylink infrastructure") Signed-off-by: James Hilliard --- drivers/net/phy/phylink.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c index e885da1c2831..2f0e3a30615c 100644 --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c @@ -3570,10 +3570,13 @@ static int phylink_phy_read(struct phylink *pl, unsigned int phy_id, return mdiobus_read(pl->phydev->mdio.bus, phy_id, reg); } -static int phylink_phy_write(struct phylink *pl, unsigned int phy_id, - unsigned int reg, unsigned int val) +static int phylink_phy_write(struct phylink *pl, struct ifreq *ifr) { + struct mii_ioctl_data *mii = if_mii(ifr); struct phy_device *phydev = pl->phydev; + u16 phy_id = mii->phy_id; + u16 reg = mii->reg_num; + u16 val = mii->val_in; int prtad, devad; if (mdio_phy_id_is_c45(phy_id)) { @@ -3608,6 +3611,10 @@ static int phylink_phy_write(struct phylink *pl, unsigned int phy_id, reg, val); } + if (phy_id == phydev->mdio.addr && reg == MII_BMCR && + (val & BMCR_RESET)) + return phy_mii_ioctl(phydev, ifr, SIOCSMIIREG); + return mdiobus_write(phydev->mdio.bus, phy_id, reg, val); } @@ -3697,8 +3704,7 @@ int phylink_mii_ioctl(struct phylink *pl, struct ifreq *ifr, int cmd) break; case SIOCSMIIREG: - ret = phylink_phy_write(pl, mii->phy_id, mii->reg_num, - mii->val_in); + ret = phylink_phy_write(pl, ifr); break; default: -- 2.53.0