On Fri, Nov 13, 2026 at 03:11:40PM +0800, Mina Hui-Min Chou wrote:
> ERRATA_ANDES_CMO depends on ARCH_R9A07G043, so it can only be enabled
> for the Renesas RZ/Five, although other Andes SoCs such as those built
> on the A27L2 need it too. Drop the dependency, and select
> ANDES_LLCACHE and CACHEMAINT_FOR_DMA so that the errata always comes
> with its cache driver, which ARCH_R9A07G043 used to guarantee.
> 
> As ERRATA_ANDES_CMO is default y, it is now also enabled in the generic
> riscv defconfig. The errata only acts on Andes cores at boot, so other
> platforms are not affected.
> 
> RZ/Five still gets uncached memory for coherent DMA allocations from the
> DMA_GLOBAL_POOL that ARCH_R9A07G043 selects. This patch only covers
> cache maintenance for streaming DMA; how other platforms provide uncached
> memory stays platform specific.
> 
> Signed-off-by: Mina Hui-Min Chou <minachou@andestech.com>
> ---
>  arch/riscv/Kconfig.errata | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
> index 4f77b3c6d7fd..3c43e065aa01 100644
> --- a/arch/riscv/Kconfig.errata
> +++ b/arch/riscv/Kconfig.errata
> @@ -12,7 +12,9 @@ config ERRATA_ANDES
>  
>  config ERRATA_ANDES_CMO
>  	bool "Apply Andes cache management errata"
> -	depends on ERRATA_ANDES && ARCH_R9A07G043
> +	depends on ERRATA_ANDES
> +	select ANDES_LLCACHE
> +	select CACHEMAINT_FOR_DMA

If you're selecting it here, can you not drop it from the renesas soc
Kconfig file?

>  	select RISCV_DMA_NONCOHERENT
>  	default y
>  	help
> -- 
> 2.34.1
>