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charset="utf-8" Message-Id: <20261113-vop2-fixes-v3-3-08ae37e83b5c@gmail.com> References: <20261113-vop2-fixes-v3-0-08ae37e83b5c@gmail.com> In-Reply-To: <20261113-vop2-fixes-v3-0-08ae37e83b5c@gmail.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Sascha Hauer Cc: Piotr Zalewski , Chaoyi Chen , Damon Ding , dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Arun Iyengar , Cristian Ciocaltea X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1794587957; l=1551; i=aiyengar1990@gmail.com; s=20261110; h=from:subject:message-id; bh=y/BLNj95neZ1kNSGI9NFsr8jsXQo+g+IgIthS+l+Duk=; b=HFnpn0UfQaUqdoo8fKpEc9f1pAJsgldamAS3CAJLhWJBsQCR4pB44jgJOoJoSQmOT/Cfg6G8M gm39pCe6xRaB8NGGqHCoLfwa5TA4YEeJfxwlZL3li41h3sXUfV2JBty X-Developer-Key: i=aiyengar1990@gmail.com; a=ed25519; pk=zXpRgUTrhaFe6jLyPqbBy3ccfkj04w0g2690Wv3mg+0= X-Endpoint-Received: by B4 Relay for aiyengar1990@gmail.com/20261110 with auth_id=1480 X-Original-From: Arun Iyengar Reply-To: aiyengar1990@gmail.com Content-Transfer-Encoding: 7bit From: Arun Iyengar rk3588_get_hdmi_pol() is passed the POLFLAG bits of the mode but tests them as DRM mode flags, so the HDMI sync polarity bits in GRF_VO1_CON0 come out wrong: +HSync/+VSync modes get one of them set and -HSync/-VSync modes none. The bits are set for a negative sync. Test the POLFLAG bits instead. Fixes: 5a028e8f062f ("drm/rockchip: vop2: Add support for rk3588") Reviewed-by: Chaoyi Chen Reviewed-by: Damon Ding Cc: Cristian Ciocaltea Signed-off-by: Arun Iyengar --- drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c index f340aba5bfd1..3e654cb99ddf 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c @@ -1683,12 +1683,13 @@ static u32 rk3588_get_mipi_port_mux(int vp_id) return 0; } -static u32 rk3588_get_hdmi_pol(u32 flags) +/* The sync polarity bits in GRF_VO1_CON0 are set for a negative sync */ +static u32 rk3588_get_hdmi_pol(u32 polflags) { u32 val; - val = (flags & DRM_MODE_FLAG_NHSYNC) ? BIT(HSYNC_POSITIVE) : 0; - val |= (flags & DRM_MODE_FLAG_NVSYNC) ? BIT(VSYNC_POSITIVE) : 0; + val = (polflags & BIT(HSYNC_POSITIVE)) ? 0 : BIT(HSYNC_POSITIVE); + val |= (polflags & BIT(VSYNC_POSITIVE)) ? 0 : BIT(VSYNC_POSITIVE); return val; } -- 2.55.0