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[86.98.194.229]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-49c60f8d66esm4680211f8f.57.2026.11.13.05.24.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Nov 2026 05:24:53 -0800 (PST) From: Alexey Charkov Date: Fri, 13 Nov 2026 17:24:40 +0400 Subject: [PATCH v7 1/4] clocksource/drivers/timer-vt8500: Add defines for magic constants X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261113-vt8500-timer-updates-v7-1-a1dcc4031b12@gmail.com> References: <20261113-vt8500-timer-updates-v7-0-a1dcc4031b12@gmail.com> In-Reply-To: <20261113-vt8500-timer-updates-v7-0-a1dcc4031b12@gmail.com> To: Alexey Charkov , Krzysztof Kozlowski , Daniel Lezcano , Thomas Gleixner , Wim Van Sebroeck , Guenter Roeck Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4597; i=alchark@gmail.com; h=from:subject:message-id; bh=EnyVwDXCZhJWH17WUOtGzbF79lP3UqVzlI+QeOXtwgE=; b=owGbwMvMwCW2adGNfoHIK0sZT6slMWR951+QUrd19pfLzkqLblypmLST4f6m2XmtfR+fux7w7 Bdv+bGWt2MiC4MYF4OlmCLL3G9LbKca8c3a5eHxFWYOKxPIEGmRBgYgYGHgy03MKzXSMdIz1TbU MzTSMdYxYuDiFICpjvFh+MPDJnIulv3pBWHtK8ytR5+9CszfKzTDNXR/zft/2S2+HE8YGSZs3/r BevexQ4oqh5pnVWZe/7HwSMEcp1/2rl3vO4TZjZkB X-Developer-Key: i=alchark@gmail.com; a=openpgp; fpr=9DF6A43D95320E9ABA4848F5B2A2D88F1059D4A5 Add defines for the timer registers and their bits to make the code more self-explanatory. While at that, replace _VAL suffixes with more intuitive _REG suffixes on register offsets. No functional changes. Signed-off-by: Alexey Charkov --- drivers/clocksource/timer-vt8500.c | 62 ++++++++++++++++++++++++-------------- 1 file changed, 39 insertions(+), 23 deletions(-) diff --git a/drivers/clocksource/timer-vt8500.c b/drivers/clocksource/timer-vt8500.c index a469b1b5f972..c4694cf8bea6 100644 --- a/drivers/clocksource/timer-vt8500.c +++ b/drivers/clocksource/timer-vt8500.c @@ -24,15 +24,28 @@ #define VT8500_TIMER_OFFSET 0x0100 #define VT8500_TIMER_HZ 3000000 -#define TIMER_MATCH_VAL 0x0000 -#define TIMER_COUNT_VAL 0x0010 -#define TIMER_STATUS_VAL 0x0014 -#define TIMER_IER_VAL 0x001c /* interrupt enable */ -#define TIMER_CTRL_VAL 0x0020 -#define TIMER_AS_VAL 0x0024 /* access status */ -#define TIMER_COUNT_R_ACTIVE (1 << 5) /* not ready for read */ -#define TIMER_COUNT_W_ACTIVE (1 << 4) /* not ready for write */ -#define TIMER_MATCH_W_ACTIVE (1 << 0) /* not ready for write */ + +#define TIMER_MATCH_REG(x) (4 * (x)) +#define TIMER_COUNT_REG 0x0010 /* clocksource counter */ + +#define TIMER_STATUS_REG 0x0014 +#define TIMER_STATUS_MATCH(x) BIT((x)) +#define TIMER_STATUS_CLEARALL (TIMER_STATUS_MATCH(0) | \ + TIMER_STATUS_MATCH(1) | \ + TIMER_STATUS_MATCH(2) | \ + TIMER_STATUS_MATCH(3)) + +#define TIMER_INT_EN_REG 0x001c /* interrupt enable */ +#define TIMER_INT_EN_MATCH(x) BIT((x)) + +#define TIMER_CTRL_REG 0x0020 +#define TIMER_CTRL_ENABLE BIT(0) /* enable clocksource counter */ +#define TIMER_CTRL_RD_REQ BIT(1) /* request counter read */ + +#define TIMER_ACC_STS_REG 0x0024 /* access status */ +#define TIMER_ACC_WR_MATCH(x) BIT((x)) /* writing Match (x) value */ +#define TIMER_ACC_WR_COUNTER BIT(4) /* writing clocksource counter */ +#define TIMER_ACC_RD_COUNTER BIT(5) /* reading clocksource counter */ #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) @@ -43,11 +56,12 @@ static void __iomem *regbase; static u64 vt8500_timer_read(struct clocksource *cs) { int loops = msecs_to_loops(10); - writel(3, regbase + TIMER_CTRL_VAL); - while ((readl((regbase + TIMER_AS_VAL)) & TIMER_COUNT_R_ACTIVE) - && --loops) + + writel(TIMER_CTRL_ENABLE | TIMER_CTRL_RD_REQ, regbase + TIMER_CTRL_REG); + while (readl(regbase + TIMER_ACC_STS_REG) & TIMER_ACC_RD_COUNTER && + --loops) cpu_relax(); - return readl(regbase + TIMER_COUNT_VAL); + return readl(regbase + TIMER_COUNT_REG); } static struct clocksource clocksource = { @@ -63,23 +77,25 @@ static int vt8500_timer_set_next_event(unsigned long cycles, { int loops = msecs_to_loops(10); u64 alarm = clocksource.read(&clocksource) + cycles; - while ((readl(regbase + TIMER_AS_VAL) & TIMER_MATCH_W_ACTIVE) - && --loops) + + while (readl(regbase + TIMER_ACC_STS_REG) & TIMER_ACC_WR_MATCH(0) && + --loops) cpu_relax(); - writel((unsigned long)alarm, regbase + TIMER_MATCH_VAL); + writel((unsigned long)alarm, regbase + TIMER_MATCH_REG(0)); if ((signed)(alarm - clocksource.read(&clocksource)) <= MIN_OSCR_DELTA) return -ETIME; - writel(1, regbase + TIMER_IER_VAL); + writel(TIMER_INT_EN_MATCH(0), regbase + TIMER_INT_EN_REG); return 0; } static int vt8500_shutdown(struct clock_event_device *evt) { - writel(readl(regbase + TIMER_CTRL_VAL) | 1, regbase + TIMER_CTRL_VAL); - writel(0, regbase + TIMER_IER_VAL); + writel(readl(regbase + TIMER_CTRL_REG) | TIMER_CTRL_ENABLE, + regbase + TIMER_CTRL_REG); + writel(0, regbase + TIMER_INT_EN_REG); return 0; } @@ -95,7 +111,7 @@ static struct clock_event_device clockevent = { static irqreturn_t vt8500_timer_interrupt(int irq, void *dev_id) { struct clock_event_device *evt = dev_id; - writel(0xf, regbase + TIMER_STATUS_VAL); + writel(TIMER_STATUS_CLEARALL, regbase + TIMER_STATUS_REG); evt->event_handler(evt); return IRQ_HANDLED; @@ -119,9 +135,9 @@ static int __init vt8500_timer_init(struct device_node *np) return -EINVAL; } - writel(1, regbase + TIMER_CTRL_VAL); - writel(0xf, regbase + TIMER_STATUS_VAL); - writel(~0, regbase + TIMER_MATCH_VAL); + writel(TIMER_CTRL_ENABLE, regbase + TIMER_CTRL_REG); + writel(TIMER_STATUS_CLEARALL, regbase + TIMER_STATUS_REG); + writel(~0, regbase + TIMER_MATCH_REG(0)); ret = clocksource_register_hz(&clocksource, VT8500_TIMER_HZ); if (ret) { -- 2.56.0