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Thu, 12 Nov 2026 16:35:34 -0800 (PST) Received: from navid-pc ([2a01:4b00:a856:6220::a11]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-49c5f1c18b9sm1703515f8f.20.2026.11.12.16.35.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Nov 2026 16:35:34 -0800 (PST) From: Navid Ghahremani To: =?utf-8?q?Stefan_D=C3=B6singer?= Cc: linux-arm-kernel@lists.infradead.org, arnd@arndb.de, krzk@kernel.org, Stephen Boyd , Brian Masney , Jerome Brunet , Philipp Zabel , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: Re: [PATCH v2 06/24] clk: zte: Add ZX279128S CRM clock and reset driver Date: Fri, 13 Nov 2026 00:35:33 +0000 Message-ID: <20261113003533.3660311-1-ghahramani.navid@gmail.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <86bpNzKYRniAzc8v_5Lpqg@gmail.com> References: <20261014072109.1759502-1-ghahramani.navid@gmail.com> <20261014072109.1759502-7-ghahramani.navid@gmail.com> <86bpNzKYRniAzc8v_5Lpqg@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hi Stefan, Stefan Dösinger wrote: > The comments I sent for v1 still apply to v2 I think. You are right. In my reply on the RFC I wrote that your points were done in v2, and for the clock driver that was wrong. It still had its own PLL code, direct MMIO and its own lock, and the resets were still in drivers/clk. > Please try to reuse the infrastructure in place for zx29. Ideally clk- > zx279128s.c should be just static data and a minimalistic _probe function that > invokes zx_clk_common_probe(). That is how the next version will do it, on v7.4-rc1, with static data for the regmap clocks and pll-zx.c, a short probe that calls zx_clk_common_probe() and the resets in a separate reset driver. My question about the MFD and reset layout is in my reply to the cover letter. Best regards, Navid