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Thu, 12 Nov 2026 16:35:55 -0800 (PST) Received: from navid-pc ([2a01:4b00:a856:6220::a11]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-49c7da37b19sm1497029f8f.5.2026.11.12.16.35.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Nov 2026 16:35:54 -0800 (PST) From: Navid Ghahremani To: =?UTF-8?q?Stefan=20D=C3=B6singer?= Cc: linux-arm-kernel@lists.infradead.org, arnd@arndb.de, krzk@kernel.org, Mark Brown , Philipp Zabel , linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org Subject: Re: [PATCH v2 20/24] spi: zx: Add ZTE ZX family SPI flash controller driver Date: Fri, 13 Nov 2026 00:35:53 +0000 Message-ID: <20261113003553.3661566-1-ghahramani.navid@gmail.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: References: <20261014072109.1759502-1-ghahramani.navid@gmail.com> <20261014072109.1759502-21-ghahramani.navid@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hi Stefan, Thanks for looking at the changes. Since you plan to submit the driver yourself, I am dropping the SPI patches from my series, so this is just to answer your questions. Stefan Dösinger wrote: > So IOW, this function should primarily configure ZX_QSPI_TIMING_REG. If the > target clock can't be achieved with the controller input clock (e.g. divider > is larger than ZX_QSPI_TIMING_REG supports or clock rate is lower than > requested SPI speed), then a change to the wclk is in order. Agreed. I only changed the wclk because that is what worked on my board, and I never checked whether ZX_QSPI_TIMING_REG has a divider. > > + ctrl->min_speed_hz = clk_round_rate(qspi->wclk, 1); > > + ctrl->max_speed_hz = 50000000; > This looks wrong - the max speed is probably the highest possible wclk rate, > the lowest speed the lowest possible wclk rate divided by the highest possible > divider. Agreed. > > + /* Ensure proper data sampling point */ > > + reg = readl_relaxed(qspi->io_base + ZX_QSPI_TIMING_REG); > > + if (!FIELD_GET(GENMASK(17, 16), reg)) { > > + reg |= FIELD_PREP(GENMASK(17, 16), 1); > > + writel_relaxed(reg, qspi->io_base + ZX_QSPI_TIMING_REG); > > + } > I don't know what this is doing. Can you elaborate? That value came over from the earlier driver I used on this board, which always wrote 1 to bits 17:16. There is no public register documentation for this SoC, so I kept it, and v2 only writes it when the field reads 0. The sampling point in the comment is my guess at what it does and I have not tried other values. If it matters for your driver, I can try 0 to 3 on my board and tell you which ones read the flash correctly. Best regards, Navid