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Thu, 12 Nov 2026 16:36:09 -0800 (PST) Received: from navid-pc ([2a01:4b00:a856:6220::a11]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-49c609c602dsm1918847f8f.46.2026.11.12.16.36.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Nov 2026 16:36:08 -0800 (PST) From: Navid Ghahremani To: =?utf-8?q?Stefan_D=C3=B6singer?= Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, arnd@arndb.de, linux@armlinux.org.uk, robh@kernel.org, krzk@kernel.org Subject: Re: [PATCH 13/24] PCI: dwc: Add ZTE ZX279128S host controller driver Date: Fri, 13 Nov 2026 00:36:07 +0000 Message-ID: <20261113003607.3662439-1-ghahramani.navid@gmail.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: References: <20261010130024.177503-1-ghahramani.navid@gmail.com> <20261010130024.177503-14-ghahramani.navid@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hi Stefan, Stefan Dösinger wrote: > If this is a clock control it would be better to write a clock driver that > manages the crm2 region and exposes a proper clock handle. That is done since v2. crm2 has its own clock and reset provider and the PCIe driver uses the clock and reset handles. > For the phy parts that are part of topcrm: drivers/phy has PCIe PHY drivers. The PHY setup moved into a PHY driver with #phy-cells on topcrm, so the PCIe driver doesn't write topcrm registers anymore. > By and large the zx279128s_pcie_init_crm has a bad code smell: It looks like > an LLM translation of ZTE's code to me without understanding what the > registers actually do. That is fair. There is no public register documentation for this SoC, so that function followed ZTE's code, and I got part of it wrong. Agustin found that two of the writes went to the wrong block and had no effect, see the v2 11/24 thread. For several of the PHY writes I only have ZTE's values and no explanation yet. I will try to work them out before the PCIe series, and the patch will say which values are just copied from ZTE. Best regards, Navid