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Thu, 12 Nov 2026 16:36:43 -0800 (PST) Received: from navid-pc ([2a01:4b00:a856:6220::a11]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4bb571f976esm3282945e9.3.2026.11.12.16.36.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Nov 2026 16:36:43 -0800 (PST) From: Navid Ghahremani To: Agustin Santiago Isasmendi Cc: linux@armlinux.org.uk, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, arnd@arndb.de, stefandoesinger@gmail.com, krzk@kernel.org, robh@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v2 0/2] ARM: l2c: honour status = "disabled" on the L2 cache node Date: Fri, 13 Nov 2026 00:36:41 +0000 Message-ID: <20261113003641.3664652-1-ghahramani.navid@gmail.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261112072953.989664-1-isasmendi.agus@gmail.com> References: <20261112072953.989664-1-isasmendi.agus@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi Agustin, I tested v2 as posted on my ZTE ZXHN H3600 with 512 MiB and an L2C-310 r3p3, running 6.18.60 with the OpenWrt patches for this board and booted with kexec. With the cache node enabled the cache comes up as before. With the node disabled the kernel reports that the L2C is disabled by the device tree and leaves the cache off, and the board ran 10 minutes of Wi-Fi receive, Ethernet send and PCIe config reads on both CPUs together without a hang. Like in my earlier test, the previous kernel had already turned the cache off before the kexec, so this does not show what the boot loader leaves, but you checked that part on your unit. Tested-by: Navid Ghahremani Best regards, Navid