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Thu, 12 Nov 2026 16:36:58 -0800 (PST) Received: from navid-pc ([2a01:4b00:a856:6220::a11]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4bb4e2adf53sm106506085e9.15.2026.11.12.16.36.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Nov 2026 16:36:57 -0800 (PST) From: Navid Ghahremani To: Andrew Lunn Cc: linux-arm-kernel@lists.infradead.org, arnd@arndb.de, stefandoesinger@gmail.com, krzk@kernel.org, Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Subject: Re: [PATCH v2 16/24] net: phy: Add Sanechips ZX5201 PHY support Date: Fri, 13 Nov 2026 00:36:55 +0000 Message-ID: <20261113003655.3665572-1-ghahramani.navid@gmail.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <788c9b01-473e-4c45-b6f0-b2ba054da8e9@lunn.ch> References: <20261014072109.1759502-1-ghahramani.navid@gmail.com> <20261014072109.1759502-17-ghahramani.navid@gmail.com> <788c9b01-473e-4c45-b6f0-b2ba054da8e9@lunn.ch> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi Andrew, Andrew Lunn wrote: > What do you get when you read registers 2 and 3 of the SERDES? Is > there an ID in them? > > If the mdio bus is scanned, and there is an ID, phylib will try to > probe a PHY driver on the SERDES. I read them on the board. Registers 0 to 3 at address 9 all read 0x0000, while addresses with nothing on them like 7, 20 and 30 read 0xffff. Something does answer at address 9 though, since registers 22 and 27 there hold the values the driver writes. So there is no ID, and no PHY driver would match ID 0. But phylib only treats an ID with all of its low 29 bits set as no device, so a bus scan would still register a PHY device at address 9. On this board the MDIO node lists its PHYs, so of_mdiobus_register() does not scan and no device shows up at address 9. > I would suggest adding a probe, and validate phydev->mdio.addr is not > 31. ENODEV, or EINVAL, to indicate the setup is invalid. Done in my tree, the probe returns -EINVAL for address 31. > It would be nice to reverse engineer what these bits do. And then add > proper LED controls. However, that can be later. OK, I will look at the LEDs later. > This says it is an RGMII PHY. Why does it have a SERDES? That suggests > SGMII? > > We need to understand this, because if it is an RGMII PHY, we need to > address the RGMII delays, which that page says it can controller. That part I still have to find out. My driver has always told phylib gmii and the WAN port runs at 1 Gbs, but I have not worked out yet what the link between the SoC and the ZX5201 really is. SerDes was just the name I gave the registers at the second address, and there is no public documentation for them. I will find out what the interface is, and how the delays are set if it is RGMII, before I send the networking patches again. Best regards, Navid