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Thu, 12 Nov 2026 16:37:04 -0800 (PST) Received: from navid-pc ([2a01:4b00:a856:6220::a11]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4bb571f6a40sm2591625e9.2.2026.11.12.16.37.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Nov 2026 16:37:04 -0800 (PST) From: Navid Ghahremani To: Andrew Lunn Cc: linux-arm-kernel@lists.infradead.org, arnd@arndb.de, stefandoesinger@gmail.com, krzk@kernel.org, Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Subject: Re: [PATCH v2 15/24] net: mdio: Add ZTE ZX279128S MDIO controller Date: Fri, 13 Nov 2026 00:37:03 +0000 Message-ID: <20261113003703.3666085-1-ghahramani.navid@gmail.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <595371a9-6b7b-4ad9-985e-66f0e659f4a1@lunn.ch> References: <20261014072109.1759502-1-ghahramani.navid@gmail.com> <20261014072109.1759502-16-ghahramani.navid@gmail.com> <595371a9-6b7b-4ad9-985e-66f0e659f4a1@lunn.ch> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi Andrew, Andrew Lunn wrote: > > + writel(0, base + ZX_MDIO_STATUS); > > + writel(readl(base + ZX_MDIO_CMD) & ~ZX_MDIO_CMD_START, > > + base + ZX_MDIO_CMD); > > This is the same as what you did at the beginning, but in the opposite > order. Is it actually needed, and can the same order be used? It is not needed. That clear came over from the first driver I wrote for this board. There is no public documentation for the MDIO block, so that driver was put together by reverse engineering, and I never checked whether every step was needed. I removed the clear after the transfer, so only the one before the start is left, and tested it on my board. All five PHYs probe with the same IDs and link states as before, and a few minutes of PHY polling plus traffic gave no MDIO timeouts. > Is this the bus clock? Does it need setting to 2.5Mhz? wclk is the MDIO block's work clock from the LSP1 clock controller. The driver sets bit 12 of the command register, which I took to be an MDC divider. The 50 MHz and 2.5 MHz in my comment are not measured, and the wclk rate is not confirmed yet either. I will find out the real MDC rate before I resend the MDIO driver and fix the comment and the code to match. > It needs a device tree binding. But that is mostly boilerplate. The binding is patch 14/24 of this series and Rob gave a Reviewed-by. The MDIO, PHY and switch patches will go to netdev as their own series like you asked. Best regards, Navid