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Thu, 12 Nov 2026 23:32:52 -0800 (PST) Received: from deb05.proceq.com ([213.160.61.66]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-49c5d223a29sm3799903f8f.8.2026.11.12.23.32.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Nov 2026 23:32:51 -0800 (PST) From: Mehmet Fide To: Andi Shyti , Oleksij Rempel Cc: Pengutronix Kernel Team , Frank Li , Sascha Hauer , Fabio Estevam , Yao Yuan , Wolfram Sang , linux-i2c@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: [PATCH 0/2] i2c: imx: two fixes for a DMA write that is not acknowledged Date: Fri, 13 Nov 2026 08:32:48 +0100 Message-ID: <20261113073250.1037215-1-mehmet.fide@gmail.com> X-Mailer: git-send-email 2.56.0 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Mehmet Fide A write of DMA_THRESHOLD bytes or more to an address that does not answer leaves the interrupt status behind, so that the next DMA read returns 0xff for every byte without an error (patch 1), and it blocks for DMA_TIMEOUT before it fails with -ETIMEDOUT instead of -ENXIO (patch 2). Patch 2 needs patch 1. Tested on a Colibri VF50 (i2c0 at 100 kHz, DMA) with v6.12.117, where the touched code is the same; on this base compile tested only (W=1, sparse). 200 rounds of failed write, 32 byte read and acknowledged 18 byte write: 200 times ENXIO at once, no wrong read, every write acknowledged. Mehmet Fide (2): i2c: imx: do not carry the interrupt status over to the next transfer i2c: imx: return -ENXIO at once when a DMA write is not acknowledged drivers/i2c/busses/i2c-imx.c | 10 ++++++++++ 1 file changed, 10 insertions(+) base-commit: 25e7ab89f4774b0f842cee0e8a20c11f755924d5 -- 2.56.0