[PATCH 0/2] iommu/amd: Optimize IRT cache invalidation for nested VM workloads

[Guanghui Feng <guanghuifeng@linux.alibaba.com>]

This series optimizes the AMD IOMMU interrupt remapping table (IRT)
cache invalidation path for nested virtualization workloads.

When IOMMU AVIC is enabled, every nested VM entry/exit that switches
interrupt routes between guest and remapping modes calls into
iommu_flush_irt_and_complete().  A reported workload with 4334 device
entries shows median lookup latencies of 22-33 us per invocation due
to a linear search_dev_data() walk, even when IRT caching is disabled
and the lookup result is unused.

Patch 1 moves the device lookup after the irtcachedis_enabled early
return, eliminating the unnecessary walk when IRT caching is off.

Patch 2 caches the device data pointer (resolved at IRQ allocation
time) in struct amd_ir_data and threads it through all IRTE update
paths: guest-mode toggle, affinity change, IRQ enable/disable, and
IRTE free.  The amd_irte_ops interface is extended to carry the
pointer, eliminating all search_dev_data() calls at runtime.

Both patches preserve DMA-alias invalidation, command ordering,
locking, and completion-wait semantics when IRT caching is enabled.

Guanghui Feng (2):
  iommu/amd: Skip device lookup when IRT caching is disabled
  iommu/amd: Reuse device data for IRTE cache invalidation

 drivers/iommu/amd/amd_iommu_types.h | 10 ++--
 drivers/iommu/amd/iommu.c           | 73 ++++++++++++++++-------------
 2 files changed, 48 insertions(+), 35 deletions(-)

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2.43.7