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Fri, 13 Nov 2026 10:54:23 +0000 (GMT) Received: from epcas5p1.samsung.com (unknown [182.195.38.90]) by epsnrtp03.localdomain (Postfix) with ESMTP id 4jQvJt4mylz3hhT4; Fri, 13 Nov 2026 10:54:22 +0000 (GMT) Received: from epsmtip2.samsung.com (unknown [182.195.34.31]) by epcas5p4.samsung.com (KnoxPortal) with ESMTPA id 20261113104858epcas5p47fb0f4e46302dfe01070f4cd298870ca~nlR9RECkE1464514645epcas5p4v; Fri, 13 Nov 2026 10:48:58 +0000 (GMT) Received: from bose.samsungds.net (unknown [107.108.83.9]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20261113104855epsmtip2bc2e23b8a4aa3305c7f3dad364b60d71~nlR618mo_2220522205epsmtip25; Fri, 13 Nov 2026 10:48:55 +0000 (GMT) From: Raghav Sharma To: krzk@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, peter.griffin@linaro.org, alim.akhtar@samsung.com, sboyd@kernel.org, bmasney+clk@redhat.com, jbrunet+clk@baylibre.com, robh@kernel.org, conor+dt@kernel.org, raghav.s@samsung.com Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, is.gandhi@samsung.com, ts.amit@samsung.com, pokala.reddy@samsung.com Subject: [PATCH v3 10/14 RESEND] clk: samsung: exynos8855: add block usb clock support Date: Fri, 13 Nov 2026 16:36:08 +0530 Message-Id: <20261113110612.3265841-11-raghav.s@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261113110612.3265841-1-raghav.s@samsung.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CMS-MailID: 20261113104858epcas5p47fb0f4e46302dfe01070f4cd298870ca X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P X-CPGSPASS: Y cpgsPolicy: CPGSC10-543,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20261113104858epcas5p47fb0f4e46302dfe01070f4cd298870ca References: <20261113110612.3265841-1-raghav.s@samsung.com> Register compatible and cmu_info data to support clocks. CMU_USB, this provides clocks for USB Co-developed-by: Alim Akhtar Signed-off-by: Alim Akhtar Signed-off-by: Raghav Sharma --- drivers/clk/samsung/clk-exynos8855.c | 77 ++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos8855.c b/drivers/clk/samsung/clk-exynos8855.c index 0be1cefadb51..87c616c8487e 100644 --- a/drivers/clk/samsung/clk-exynos8855.c +++ b/drivers/clk/samsung/clk-exynos8855.c @@ -20,11 +20,13 @@ #define CLKS_NR_PERIC (CLK_GOUT_USI_PERIC + 1) #define CLKS_NR_PERIS (CLK_GOUT_WDT1_PERIS + 1) #define CLKS_NR_HSI (CLK_GOUT_UFS_EMBD_UNIPRO_HSI + 1) +#define CLKS_NR_USB (CLK_GOUT_SYSREG_USB + 1) #define EXYNOS8855_HSI_GATE_DBG_OFFSET 0x2000 #define EXYNOS8855_PERIS_GATE_DBG_OFFSET 0x2004 #define EXYNOS8855_PERIC_GATE_DBG_OFFSET 0x2024 #define EXYNOS8855_TOP_GATE_DBG_OFFSET 0x20A0 +#define EXYNOS8855_USB_GATE_DBG_OFFSET 0x2004 #define EXYNOS8855_DRCG_EN_OFFSET 0x104 #define EXYNOS8855_MEMCLK_OFFSET 0x108 @@ -1257,6 +1259,78 @@ static const struct samsung_cmu_info hsi_cmu_info __initconst = { .memclk_offset = EXYNOS8855_MEMCLK_OFFSET, }; +/* ---- CMU_USB --------------------------------------------------------- */ + +/* Register Offset definitions for CMU_USB (0x13000000) */ +#define CMU_USB_PLL_CON0_MUX_CLKCMU_USB_NOC_USER 0x600 +#define CMU_USB_PLL_CON0_MUX_CLKCMU_USB_USB20DRD_USER 0x610 +#define CMU_USB_CLK_CON_MUX_CLK_USB_USB20DRD 0x1000 +#define CMU_USB_CLK_CON_DIV_CLK_USB_NOC_DIV3 0x1800 +#define CMU_USB_CLK_CON_GAT_BLK_USB_UID_CMU_USB_IPCLKPORT_PCLK 0x2000 +#define CMU_USB_CLK_CON_GAT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK 0x2030 +#define CMU_USB_CONTROLLER_OPTION0_CMU_CTRL 0x800 + +static const unsigned long usb_clk_regs[] __initconst = { + CMU_USB_PLL_CON0_MUX_CLKCMU_USB_NOC_USER, + CMU_USB_PLL_CON0_MUX_CLKCMU_USB_USB20DRD_USER, + CMU_USB_CLK_CON_MUX_CLK_USB_USB20DRD, + CMU_USB_CLK_CON_DIV_CLK_USB_NOC_DIV3, + CMU_USB_CLK_CON_GAT_BLK_USB_UID_CMU_USB_IPCLKPORT_PCLK, + CMU_USB_CLK_CON_GAT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK, + CMU_USB_CONTROLLER_OPTION0_CMU_CTRL, +}; + +/* List of parent clocks for Muxes in CMU_USB */ +PNAME(mout_clkcmu_usb_noc_user_p) = { "oscclk", "dout_clkcmu_usb_noc" }; +PNAME(mout_clkcmu_usb_usb20drd_user_p) = { "oscclk", "dout_clkcmu_usb_usb20drd" }; +PNAME(mout_clk_usb_usb20drd_p) = { "oscclk_usb_link", "mout_clkcmu_usb_usb20drd_user" }; + +static const struct samsung_mux_clock usb_mux_clks[] __initconst = { + MUX(CLK_MOUT_USB_NOC_USER, "mout_clkcmu_usb_noc_user", + mout_clkcmu_usb_noc_user_p, CMU_USB_PLL_CON0_MUX_CLKCMU_USB_NOC_USER, 4, 1), + MUX(CLK_MOUT_USB_USB20DRD_USER, "mout_clkcmu_usb_usb20drd_user", + mout_clkcmu_usb_usb20drd_user_p, CMU_USB_PLL_CON0_MUX_CLKCMU_USB_USB20DRD_USER, 4, 1), + MUX(CLK_MOUT_USB_USB20DRD, "mout_clk_usb_usb20drd", + mout_clk_usb_usb20drd_p, CMU_USB_CLK_CON_MUX_CLK_USB_USB20DRD, 0, 1), +}; + +static const struct samsung_div_clock usb_div_clks[] __initconst = { + DIV(CLK_DOUT_USB_NOC_DIV3, "dout_clkcmu_usb_noc_div3", + "mout_clkcmu_usb_noc_user", CMU_USB_CLK_CON_DIV_CLK_USB_NOC_DIV3, + 0, 4), +}; + +static const struct samsung_gate_clock usb_gate_clks[] __initconst = { + GATE(CLK_GOUT_CMU_USB, "gout_cmu_usb", + "mout_clkcmu_usb_noc_user", + CMU_USB_CLK_CON_GAT_BLK_USB_UID_CMU_USB_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_SYSREG_USB, "gout_sysreg_usb", + "mout_clkcmu_usb_noc_user", + CMU_USB_CLK_CON_GAT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK, + 21, 0, 0), +}; + +static const struct samsung_cmu_info usb_cmu_info __initconst = { + .mux_clks = usb_mux_clks, + .nr_mux_clks = ARRAY_SIZE(usb_mux_clks), + .div_clks = usb_div_clks, + .nr_div_clks = ARRAY_SIZE(usb_div_clks), + .gate_clks = usb_gate_clks, + .nr_gate_clks = ARRAY_SIZE(usb_gate_clks), + .nr_clk_ids = CLKS_NR_USB, + .clk_regs = usb_clk_regs, + .nr_clk_regs = ARRAY_SIZE(usb_clk_regs), + .sysreg_clk_regs = dcrg_memclk_sysreg, + .nr_sysreg_clk_regs = ARRAY_SIZE(dcrg_memclk_sysreg), + .clk_name = "bus", + .auto_clock_gate = true, + .gate_dbg_offset = EXYNOS8855_USB_GATE_DBG_OFFSET, + .option_offset = CMU_USB_CONTROLLER_OPTION0_CMU_CTRL, + .drcg_offset = EXYNOS8855_DRCG_EN_OFFSET, + .memclk_offset = EXYNOS8855_MEMCLK_OFFSET, +}; + static int __init exynos8855_cmu_probe(struct platform_device *pdev) { const struct samsung_cmu_info *info; @@ -1281,6 +1355,9 @@ static const struct of_device_id exynos8855_cmu_of_match[] = { }, { .compatible = "samsung,exynos8855-cmu-top", .data = &top_cmu_info, + }, { + .compatible = "samsung,exynos8855-cmu-usb", + .data = &usb_cmu_info, }, { } }; -- 2.34.1