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Fri, 13 Nov 2026 04:18:56 -0800 (PST) Received: from threads.localdomain ([84.70.166.92]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-49c605e5b2fsm5167103f8f.40.2026.11.13.04.18.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Nov 2026 04:18:55 -0800 (PST) From: Lucas Tanure To: xianwei.zhao@amlogic.com, Andrew Lunn , davem@davemloft.net, Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 3/7] net: stmmac: dwmac-meson8b: add support for the Amlogic T7 Date: Fri, 13 Nov 2026 12:18:48 +0000 Message-ID: <20261113121852.334604-4-tanure@linux.com> X-Mailer: git-send-email 2.56.1 In-Reply-To: <20261113121852.334604-1-tanure@linux.com> References: <20261113121852.334604-1-tanure@linux.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The glue registers on the T7 are laid out exactly as the G12A ones, RX delay field included, so the T7 can reuse the G12A settings. What it does not share is how the controller reaches memory. That path runs through a pipeline stage with a gate of its own, and no other device has any use for that gate. Nothing claims it, so it is switched off as unused and a transfer that has started can never finish. Without that gate the controller cannot do DMA at all, so it is required rather than optional: a clear probe failure beats an undiagnosable hang later. Reviewed-by: Neil Armstrong Reviewed-by: Maxime Chevallier Reviewed-by: Martin Blumenstingl Signed-off-by: Lucas Tanure --- .../ethernet/stmicro/stmmac/dwmac-meson8b.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c index 2ad70f0dc4a3..ad30730db57f 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c @@ -81,6 +81,7 @@ struct meson8b_dwmac; struct meson8b_dwmac_data { int (*set_phy_mode)(struct meson8b_dwmac *dwmac); bool has_prg_eth1_rgmii_rx_delay; + bool has_pipeline_clk; }; struct meson8b_dwmac { @@ -384,6 +385,7 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) struct plat_stmmacenet_data *plat_dat; struct stmmac_resources stmmac_res; struct meson8b_dwmac *dwmac; + struct clk *pipeline_clk; int ret; ret = stmmac_get_platform_resources(pdev, &stmmac_res); @@ -443,6 +445,13 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) if (IS_ERR(dwmac->timing_adj_clk)) return PTR_ERR(dwmac->timing_adj_clk); + if (dwmac->data->has_pipeline_clk) { + pipeline_clk = devm_clk_get_enabled(dwmac->dev, "pipeline"); + if (IS_ERR(pipeline_clk)) + return dev_err_probe(dwmac->dev, PTR_ERR(pipeline_clk), + "missing pipeline clock\n"); + } + ret = meson8b_init_rgmii_delays(dwmac); if (ret) return ret; @@ -479,6 +488,12 @@ static const struct meson8b_dwmac_data meson_g12a_dwmac_data = { .has_prg_eth1_rgmii_rx_delay = true, }; +static const struct meson8b_dwmac_data meson_t7_dwmac_data = { + .set_phy_mode = meson_axg_set_phy_mode, + .has_prg_eth1_rgmii_rx_delay = true, + .has_pipeline_clk = true, +}; + static const struct of_device_id meson8b_dwmac_match[] = { { .compatible = "amlogic,meson8b-dwmac", @@ -500,6 +515,10 @@ static const struct of_device_id meson8b_dwmac_match[] = { .compatible = "amlogic,meson-g12a-dwmac", .data = &meson_g12a_dwmac_data, }, + { + .compatible = "amlogic,t7-dwmac", + .data = &meson_t7_dwmac_data, + }, { } }; MODULE_DEVICE_TABLE(of, meson8b_dwmac_match); -- 2.56.1