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Fri, 13 Nov 2026 06:57:28 -0800 (PST) Received: from xeon ([188.163.112.62]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c5095b2369asm109937066b.25.2026.11.13.06.57.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Nov 2026 06:57:27 -0800 (PST) From: Svyatoslav Ryhel To: Prashant Gaikwad , Stephen Boyd , Brian Masney , Jerome Brunet , Thierry Reding , Jonathan Hunter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mikko Perttunen , Svyatoslav Ryhel Cc: linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v1 0/2] clk: tegra114: Add CSI pad clock gates Date: Fri, 13 Nov 2026 16:57:06 +0200 Message-ID: <20261113145708.261530-1-clamor95@gmail.com> X-Mailer: git-send-email 2.53.0 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Tegra114 has CSI pad bits in both PLLD and PLLD2 clocks that are required for the correct work of the CSI block. Add CSI pad A and pad B clock gates with PLLD/PLLD2 parents, respectively. This change is similar to Tegra30 pad clocks and is required for CSI block. Svyatoslav Ryhel (2): dt-bindings: clock: tegra114: Add IDs for CSI pad clocks clk: tegra114: Add CSI pad clock gates drivers/clk/tegra/clk-tegra114.c | 11 +++++++++++ include/dt-bindings/clock/tegra114-car.h | 3 ++- 2 files changed, 13 insertions(+), 1 deletion(-) -- 2.53.0