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Fri, 13 Nov 2026 06:57:29 -0800 (PST) Received: from xeon ([188.163.112.62]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c5095b2369asm109937066b.25.2026.11.13.06.57.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Nov 2026 06:57:28 -0800 (PST) From: Svyatoslav Ryhel To: Prashant Gaikwad , Stephen Boyd , Brian Masney , Jerome Brunet , Thierry Reding , Jonathan Hunter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mikko Perttunen , Svyatoslav Ryhel Cc: linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v1 1/2] dt-bindings: clock: tegra114: Add IDs for CSI pad clocks Date: Fri, 13 Nov 2026 16:57:07 +0200 Message-ID: <20261113145708.261530-2-clamor95@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261113145708.261530-1-clamor95@gmail.com> References: <20261113145708.261530-1-clamor95@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Tegra114 has CSI pad clock enable bits embedded into PLLD/PLLD2 registers. Add ids for these clocks. Additionally, move TEGRA114_CLK_CLK_MAX into clk-tegra114 source. Signed-off-by: Svyatoslav Ryhel --- drivers/clk/tegra/clk-tegra114.c | 1 + include/dt-bindings/clock/tegra114-car.h | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index 97f5500b13b5f..80b7f64125d92 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -47,6 +47,7 @@ #define CPU_FINETRIM_R_FCPU_6_MASK (0x3 << CPU_FINETRIM_R_FCPU_6_SHIFT) #define TEGRA114_CLK_PERIPH_BANKS 5 +#define TEGRA114_CLK_CLK_MAX 314 #define PLLC_BASE 0x80 #define PLLC_MISC2 0x88 diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h index a93426f008acc..b53f5942f4bae 100644 --- a/include/dt-bindings/clock/tegra114-car.h +++ b/include/dt-bindings/clock/tegra114-car.h @@ -341,6 +341,7 @@ #define TEGRA114_CLK_DSIA_MUX 309 #define TEGRA114_CLK_DSIB_MUX 310 #define TEGRA114_CLK_XUSB_SS_DIV2 311 -#define TEGRA114_CLK_CLK_MAX 312 +#define TEGRA114_CLK_CSIA_PAD 312 +#define TEGRA114_CLK_CSIB_PAD 313 #endif /* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */ -- 2.53.0