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Fri, 13 Nov 2026 06:57:31 -0800 (PST) Received: from xeon ([188.163.112.62]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c5095b2369asm109937066b.25.2026.11.13.06.57.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Nov 2026 06:57:30 -0800 (PST) From: Svyatoslav Ryhel To: Prashant Gaikwad , Stephen Boyd , Brian Masney , Jerome Brunet , Thierry Reding , Jonathan Hunter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mikko Perttunen , Svyatoslav Ryhel Cc: linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v1 2/2] clk: tegra114: Add CSI pad clock gates Date: Fri, 13 Nov 2026 16:57:08 +0200 Message-ID: <20261113145708.261530-3-clamor95@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261113145708.261530-1-clamor95@gmail.com> References: <20261113145708.261530-1-clamor95@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Tegra114 has CSI pad bits in both PLLD and PLLD2 clocks that are required for the correct work of the CSI block. Add CSI pad A and pad B clock gates with PLLD/PLLD2 parents, respectively. Signed-off-by: Svyatoslav Ryhel --- drivers/clk/tegra/clk-tegra114.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index 80b7f64125d92..e3d8ab76db649 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -1041,6 +1041,16 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base, 0, 82, periph_clk_enb_refcnt); clks[TEGRA114_CLK_DSIB] = clk; + /* csia_pad */ + clk = clk_register_gate(NULL, "csia_pad", "pll_d", CLK_SET_RATE_PARENT, + clk_base + PLLD_BASE, 26, 0, &pll_d_lock); + clks[TEGRA114_CLK_CSIA_PAD] = clk; + + /* csib_pad */ + clk = clk_register_gate(NULL, "csib_pad", "pll_d2", CLK_SET_RATE_PARENT, + clk_base + PLLD2_BASE, 26, 0, &pll_d2_lock); + clks[TEGRA114_CLK_CSIB_PAD] = clk; + /* csus */ clk = tegra_clk_register_periph_gate("csus", "vi_sensor", 0, clk_base, 0, TEGRA114_CLK_CSUS, -- 2.53.0