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Fri, 13 Nov 2026 08:18:46 -0800 (PST) Received: from xeon ([188.163.112.62]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c5095b24b88sm122297266b.16.2026.11.13.08.18.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Nov 2026 08:18:45 -0800 (PST) From: Svyatoslav Ryhel To: Thierry Reding , Jonathan Hunter , Sowjanya Komatineni , Luca Ceresoli , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mauro Carvalho Chehab , Greg Kroah-Hartman , Svyatoslav Ryhel , Mikko Perttunen , Hans Verkuil , Sakari Ailus , Cong Nguyen , Faisal Mukhtar , Dan Carpenter , Hungyu Lin , Hao-Qun Huang , Yury Norov , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: linux-media@vger.kernel.org, linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH v1 03/10] media: tegra-video: vi: Diverge Tegra20 and Tegra30 VI SoC descriptions Date: Fri, 13 Nov 2026 18:18:12 +0200 Message-ID: <20261113161819.36847-4-clamor95@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261113161819.36847-1-clamor95@gmail.com> References: <20261113161819.36847-1-clamor95@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Further investigation shows that the current maximum VI clock rate is too high for Tegra20 and is better suited for Tegra30. The correct clock frequency for Tegra20 should be 150 MHz, as it was set prior to the addition of Tegra30 VI support — a value backed up by the current Tegra20 peripheral OPP table. Tegra30 supports up to 470 MHz for the VI clock, but this rate is available only on higher-end Tegra30 SoC variants. The highest clock rate supported across all SoC variants is 300 MHz. Diverge the Tegra20 and Tegra30 VI SoC descriptions to account for maximum VI clock limits, setting 150 MHz for Tegra20 and 300 MHz for Tegra30. Additionally, remove the APB_MISC workaround for Tegra30, as it is Tegra20 specific. Fixes: 071fa83ded5e ("staging: media: tegra-video: tegra20: increase maximum VI clock frequency") Signed-off-by: Svyatoslav Ryhel --- .../platform/nvidia/tegra-video/tegra20.c | 22 ++++++++++++++++++- .../media/platform/nvidia/tegra-video/vi.c | 5 ++++- .../media/platform/nvidia/tegra-video/vi.h | 5 ++++- .../media/platform/nvidia/tegra-video/video.c | 3 ++- 4 files changed, 31 insertions(+), 4 deletions(-) diff --git a/drivers/media/platform/nvidia/tegra-video/tegra20.c b/drivers/media/platform/nvidia/tegra-video/tegra20.c index cdadff98eae75..f27ecb1ba29a7 100644 --- a/drivers/media/platform/nvidia/tegra-video/tegra20.c +++ b/drivers/media/platform/nvidia/tegra-video/tegra20.c @@ -809,6 +809,15 @@ static const struct tegra_vi_ops tegra20_vi_ops = { .vi_stop_streaming = tegra20_vi_stop_streaming, }; +static const struct tegra_vi_ops tegra30_vi_ops = { + .channel_host1x_syncpt_init = tegra20_channel_host1x_syncpt_init, + .channel_host1x_syncpt_free = tegra20_channel_host1x_syncpt_free, + .vi_fmt_align = tegra20_fmt_align, + .channel_queue_setup = tegra20_channel_queue_setup, + .vi_start_streaming = tegra20_vi_start_streaming, + .vi_stop_streaming = tegra20_vi_stop_streaming, +}; + #define TEGRA20_VIDEO_FMT(DATA_TYPE, BIT_WIDTH, MBUS_CODE, BPP, FOURCC) \ { \ .img_dt = TEGRA_IMAGE_DT_##DATA_TYPE, \ @@ -852,7 +861,18 @@ const struct tegra_vi_soc tegra20_vi_soc = { .ops = &tegra20_vi_ops, .hw_revision = 1, .vi_max_channels = 2, /* TEGRA_VI_OUT_1 and TEGRA_VI_OUT_2 */ - .vi_max_clk_hz = 450000000, + .vi_max_clk_hz = 150000000, + .has_h_v_flip = true, +}; + +const struct tegra_vi_soc tegra30_vi_soc = { + .video_formats = tegra20_video_formats, + .nformats = ARRAY_SIZE(tegra20_video_formats), + .default_video_format = &tegra20_video_formats[0], + .ops = &tegra30_vi_ops, + .hw_revision = 1, + .vi_max_channels = 2, + .vi_max_clk_hz = 300000000, .has_h_v_flip = true, }; diff --git a/drivers/media/platform/nvidia/tegra-video/vi.c b/drivers/media/platform/nvidia/tegra-video/vi.c index d8c77d1290efd..12eaa89304e84 100644 --- a/drivers/media/platform/nvidia/tegra-video/vi.c +++ b/drivers/media/platform/nvidia/tegra-video/vi.c @@ -1935,9 +1935,12 @@ static void tegra_vi_remove(struct platform_device *pdev) } static const struct of_device_id tegra_vi_of_id_table[] = { -#if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC) +#if defined(CONFIG_ARCH_TEGRA_2x_SOC) { .compatible = "nvidia,tegra20-vi", .data = &tegra20_vi_soc }, #endif +#if defined(CONFIG_ARCH_TEGRA_3x_SOC) + { .compatible = "nvidia,tegra30-vi", .data = &tegra30_vi_soc }, +#endif #if defined(CONFIG_ARCH_TEGRA_210_SOC) { .compatible = "nvidia,tegra210-vi", .data = &tegra210_vi_soc }, #endif diff --git a/drivers/media/platform/nvidia/tegra-video/vi.h b/drivers/media/platform/nvidia/tegra-video/vi.h index 46328e488aa38..ff5c9deed4c88 100644 --- a/drivers/media/platform/nvidia/tegra-video/vi.h +++ b/drivers/media/platform/nvidia/tegra-video/vi.h @@ -292,9 +292,12 @@ struct tegra_video_format { u32 fourcc; }; -#if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC) +#if defined(CONFIG_ARCH_TEGRA_2x_SOC) extern const struct tegra_vi_soc tegra20_vi_soc; #endif +#if defined(CONFIG_ARCH_TEGRA_3x_SOC) +extern const struct tegra_vi_soc tegra30_vi_soc; +#endif #if defined(CONFIG_ARCH_TEGRA_210_SOC) extern const struct tegra_vi_soc tegra210_vi_soc; #endif diff --git a/drivers/media/platform/nvidia/tegra-video/video.c b/drivers/media/platform/nvidia/tegra-video/video.c index 2e84385708bac..d483fb709d127 100644 --- a/drivers/media/platform/nvidia/tegra-video/video.c +++ b/drivers/media/platform/nvidia/tegra-video/video.c @@ -123,13 +123,14 @@ static void host1x_video_remove(struct host1x_device *dev) static const struct of_device_id host1x_video_subdevs[] = { #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC) { .compatible = "nvidia,tegra20-vip", }, - { .compatible = "nvidia,tegra20-vi", }, #endif #if defined(CONFIG_ARCH_TEGRA_2x_SOC) { .compatible = "nvidia,tegra20-csi", }, + { .compatible = "nvidia,tegra20-vi", }, #endif #if defined(CONFIG_ARCH_TEGRA_3x_SOC) { .compatible = "nvidia,tegra30-csi", }, + { .compatible = "nvidia,tegra30-vi", }, #endif #if defined(CONFIG_ARCH_TEGRA_210_SOC) { .compatible = "nvidia,tegra210-csi", }, -- 2.53.0