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Fri, 13 Nov 2026 08:18:53 -0800 (PST) Received: from xeon ([188.163.112.62]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c5095b24b88sm122297266b.16.2026.11.13.08.18.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Nov 2026 08:18:53 -0800 (PST) From: Svyatoslav Ryhel To: Thierry Reding , Jonathan Hunter , Sowjanya Komatineni , Luca Ceresoli , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mauro Carvalho Chehab , Greg Kroah-Hartman , Svyatoslav Ryhel , Mikko Perttunen , Hans Verkuil , Sakari Ailus , Cong Nguyen , Faisal Mukhtar , Dan Carpenter , Hungyu Lin , Hao-Qun Huang , Yury Norov , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: linux-media@vger.kernel.org, linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH v1 07/10] dt-bindings: display: tegra: Document Tegra114 CSI Date: Fri, 13 Nov 2026 18:18:16 +0200 Message-ID: <20261113161819.36847-8-clamor95@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261113161819.36847-1-clamor95@gmail.com> References: <20261113161819.36847-1-clamor95@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add a separate compatible string for the Tegra114 CSI, as it has a different programming model, uses three additional clocks, and does not contain MIPI calibration logic. Signed-off-by: Svyatoslav Ryhel --- .../display/tegra/nvidia,tegra20-csi.yaml | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml index a1aea9590769f..0c18ac81c6d6f 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml @@ -14,6 +14,7 @@ properties: enum: - nvidia,tegra20-csi - nvidia,tegra30-csi + - nvidia,tegra114-csi reg: maxItems: 1 @@ -24,12 +25,18 @@ properties: - description: module clock - description: PAD A clock - description: PAD B clock + - description: A/B lanes clock + - description: C/D lanes clock + - description: E lane clock clock-names: items: - const: csi - const: csia-pad - const: csib-pad + - const: cilab + - const: cilcd + - const: cile avdd-dsi-csi-supply: description: DSI/CSI power supply. Must supply 1.2 V. @@ -125,6 +132,22 @@ allOf: clock-names: minItems: 3 + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra114-csi + then: + properties: + "#nvidia,mipi-calibrate-cells": false + + clocks: + minItems: 6 + + clock-names: + minItems: 6 + additionalProperties: false required: -- 2.53.0