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From: Andrew Morton <akpm@linux-foundation.org>
To: Jason Gunthorpe <jgg@nvidia.com>
Cc: "Gregory Price (Meta)" <gourry@gourry.net>,
	linux-mm@kvack.org, linux-kernel@vger.kernel.org,
	kernel-team@meta.com, leon@kernel.org, david@kernel.org,
	kas@kernel.org, dave.hansen@linux.intel.com, bp@alien8.de,
	rppt@kernel.org, stable@vger.kernel.org,
	"Lorenzo Stoakes (ARM)" <ljs@kernel.org>
Subject: Re: [PATCH] mm/hmm: reject shadow-stack mappings
Date: Fri, 13 Nov 2026 18:10:25 -0800	[thread overview]
Message-ID: <20261113181025.6e8b9475b29c13d29f59e02e@linux-foundation.org> (raw)
In-Reply-To: <20261114002027.GE3706007@nvidia.com>

On Fri, 13 Nov 2026 20:20:27 -0400 Jason Gunthorpe <jgg@nvidia.com> wrote:

> On Fri, Nov 13, 2026 at 03:41:33PM -0500, Gregory Price (Meta) wrote:
> > On 2026-11-13 16:03 -0400, Jason Gunthorpe wrote:
> > > On Fri, Nov 13, 2026 at 02:55:36PM -0500, Gregory Price (Meta) wrote:
> > > > HMM can grant ordinary device write access to a userspace shadow stack.
> > > > On x86, pte_write() is true for a shadow-stack PTE, so a populated page
> > > > can be returned with HMM_PFN_WRITE without taking a CPU write fault.
> > > 
> > > I'm not sure I understand this? The pte is writable but you don't want
> > > only DMA to write to it?
> > >
> > > Is there something special on x86 that makes the shadow stack pte
> > > non-writable by the CPU?
> > >
> > 
> > Some of the context is here:
> > https://lore.kernel.org/all/20261111-mason-migrate-et-al-fixes-v1-10-3d2454362e8d@kernel.org/
> > 
> > We had a similar issue with migration, but this should handle the DMA
> > case as well.
> > 
> > It's "technically writable" but the kernel is supposed to prevent that.
> 
> Bah, it's not writable at all. The CPU PTE has write disabled and
> someone thought it was a good idea to make pte_write() return true
> because the CPU allows writes through a special instruction on this
> special PTE? So now all the places like this think its writable, when
> it really isn't.
> 
> You could also fix this by having something like pte_real_write() or
> whatever that doesn't lie about the write bit in the PTE :|
> 
> The patch is still fine, in that it matches what everything else does,
> but I'd include these details someplace..

How does this look for an altered changelog?

: On x86, a shadow-stack PTE has its ordinary write bit clear.  The CPU
: rejects ordinary stores to it, but pte_write() reports it writable because
: shadow-stack instructions can write it.  HMM consequently sets
: HMM_PFN_WRITE, which Nouveau turns into ordinary GPU write permission.  A
: process with GPU access can then overwrite its own shadow stack,
: potentially corrupting return addresses or bypassing that protection.
: 
: Reject shadow-stack VMAs in hmm_vma_walk_test(), including read access.  A
: requested fault returns -EFAULT; a snapshot records HMM_PFN_ERROR.

  reply	other threads:[~2026-11-14  2:10 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-13 19:55 Gregory Price (Meta)
2026-11-13 19:57 ` Lorenzo Stoakes (ARM)
2026-11-13 20:15   ` Gregory Price (Meta)
2026-11-13 20:03 ` Jason Gunthorpe
2026-11-13 20:41   ` Gregory Price (Meta)
2026-11-14  0:20     ` Jason Gunthorpe
2026-11-14  2:10       ` Andrew Morton [this message]
2026-11-13 20:03 ` David Hildenbrand (Arm)
2026-11-13 20:42   ` Gregory Price (Meta)
2026-11-13 21:19     ` David Hildenbrand (Arm)

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