From: Ian Rogers <irogers@google.com>
To: Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>, Jiri Olsa <jolsa@kernel.org>,
Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>,
James Clark <james.clark@linaro.org>
Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v2 10/16] perf pmu: Probe interrupt registers that require precise sampling
Date: Fri, 13 Nov 2026 11:55:55 -0800 [thread overview]
Message-ID: <20261113195601.2872738-11-irogers@google.com> (raw)
In-Reply-To: <20261113195601.2872738-1-irogers@google.com>
Some interrupt registers can only be sampled with precise sampling, for
example on x86 the XMM registers are captured in PEBS records and
x86_pmu_hw_config() rejects them in sample_regs_intr without precise_ip.
The interrupt register probe tried precise sampling as a fallback, or
for the legacy extended registers unconditionally, so the probed mask
didn't show which registers require it.
Add probe_regs_open() that opens without precise sampling first and
records when only the precise open succeeds, and record the interrupt
registers and SIMD register classes that require precise sampling in
intr_regs_precise_mask, intr_simd_precise_mask and
intr_pred_precise_mask.
Signed-off-by: Ian Rogers <irogers@google.com>
---
tools/perf/util/pmu.c | 117 +++++++++++++++++++++++++++---------------
tools/perf/util/pmu.h | 16 ++++++
2 files changed, 92 insertions(+), 41 deletions(-)
diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c
index cf1bf1a871e9..80159358318e 100644
--- a/tools/perf/util/pmu.c
+++ b/tools/perf/util/pmu.c
@@ -3397,18 +3397,50 @@ static void probe_sample_types(struct perf_pmu *pmu,
pmu->probed.can_weight = !!(pmu->probed.sample_types & PERF_SAMPLE_WEIGHT);
}
+/*
+ * Open @attr, if that fails and @try_precise then retry with precise sampling,
+ * setting @needs_precise when only the precise open succeeds. Returns whether
+ * either open succeeded.
+ */
+static bool probe_regs_open(struct perf_event_attr *attr, pid_t pid, int cpu,
+ unsigned long flags, bool try_precise, bool *needs_precise)
+{
+ u8 precise_ip = attr->precise_ip;
+ int fd = sys_perf_event_open(attr, pid, cpu, -1, flags);
+
+ *needs_precise = false;
+ if (fd < 0 && try_precise && !precise_ip) {
+ attr->precise_ip = 1;
+ fd = sys_perf_event_open(attr, pid, cpu, -1, flags);
+ attr->precise_ip = precise_ip;
+ *needs_precise = fd >= 0;
+ }
+ if (fd < 0)
+ return false;
+ close(fd);
+ return true;
+}
+
/*
* Probe supported general-purpose, extended GPR, and SIMD vector/predicate
* register sampling masks for either PERF_SAMPLE_REGS_USER (!@intr) or
- * PERF_SAMPLE_REGS_INTR (@intr).
+ * PERF_SAMPLE_REGS_INTR (@intr). For interrupt registers, the registers and
+ * register classes that can only be sampled with precise sampling are
+ * recorded in @out_precise_mask, @out_simd_precise_mask and
+ * @out_pred_precise_mask, which may be NULL for user registers.
*/
static void probe_pmu_regs_one(const struct perf_pmu *pmu,
const struct perf_event_attr *base_attr,
pid_t pid, int cpu, unsigned long flags,
int max_precise, bool intr,
u64 *out_mask, int *out_abi,
- u64 *out_simd_mask, u64 *out_pred_mask)
+ u64 *out_simd_mask, u64 *out_pred_mask,
+ u64 *out_precise_mask, u64 *out_simd_precise_mask,
+ u64 *out_pred_precise_mask)
{
+ bool try_precise = intr && max_precise > 0;
+ u64 precise_mask = 0, simd_precise_mask = 0, pred_precise_mask = 0;
+ bool needs_precise;
int dummy_abi = -1;
u64 gpr_mask = intr ? perf_intr_reg_mask(EM_HOST, &dummy_abi) :
perf_user_reg_mask(EM_HOST, &dummy_abi);
@@ -3479,14 +3511,11 @@ static void probe_pmu_regs_one(const struct perf_pmu *pmu,
else
e_attr.sample_regs_user = ext_gpr_mask;
- fd = sys_perf_event_open(&e_attr, pid, cpu, -1, flags);
- if (fd < 0 && intr && max_precise > 0) {
- e_attr.precise_ip = 1;
- fd = sys_perf_event_open(&e_attr, pid, cpu, -1, flags);
- }
- if (fd >= 0) {
- close(fd);
+ if (probe_regs_open(&e_attr, pid, cpu, flags, try_precise,
+ &needs_precise)) {
mask |= ext_gpr_mask;
+ if (needs_precise)
+ precise_mask |= ext_gpr_mask;
abi |= PERF_SAMPLE_REGS_ABI_SIMD;
ext_batch_ok = true;
}
@@ -3495,22 +3524,16 @@ static void probe_pmu_regs_one(const struct perf_pmu *pmu,
for (int b = 0; b < 64; b++) {
if (!(ext_gpr_mask & BIT_ULL(b)))
continue;
- e_attr.precise_ip = base_attr->precise_ip;
if (intr)
e_attr.sample_regs_intr = BIT_ULL(b);
else
e_attr.sample_regs_user = BIT_ULL(b);
- fd = sys_perf_event_open(&e_attr, pid, cpu, -1, flags);
- if (fd < 0 && intr && max_precise > 0) {
- e_attr.precise_ip = 1;
- fd = sys_perf_event_open(&e_attr, pid, cpu, -1,
- flags);
- }
- if (fd >= 0) {
- close(fd);
- mask |= BIT_ULL(b);
- abi |= PERF_SAMPLE_REGS_ABI_SIMD;
- }
+ if (!probe_regs_open(&e_attr, pid, cpu, flags,
+ try_precise, &needs_precise))
+ continue;
+ mask |= BIT_ULL(b);
+ precise_mask |= needs_precise ? BIT_ULL(b) : 0;
+ abi |= PERF_SAMPLE_REGS_ABI_SIMD;
}
}
}
@@ -3521,7 +3544,7 @@ static void probe_pmu_regs_one(const struct perf_pmu *pmu,
u64 class_mask = intr ?
perf_intr_simd_reg_class_mask(EM_HOST, pred) :
perf_user_simd_reg_class_mask(EM_HOST, pred);
- u64 supported_classes = 0;
+ u64 supported_classes = 0, precise_classes = 0;
for (int reg_c = 0; reg_c < 64; reg_c++) {
struct perf_event_attr s_attr = *base_attr;
@@ -3557,22 +3580,22 @@ static void probe_pmu_regs_one(const struct perf_pmu *pmu,
s_attr.sample_simd_vec_reg_user = bitmap;
}
- fd = sys_perf_event_open(&s_attr, pid, cpu, -1, flags);
- if (fd < 0 && intr && max_precise > 0) {
- s_attr.precise_ip = 1;
- fd = sys_perf_event_open(&s_attr, pid, cpu, -1, flags);
- }
- if (fd >= 0) {
- close(fd);
+ if (probe_regs_open(&s_attr, pid, cpu, flags, try_precise,
+ &needs_precise)) {
supported_classes |= BIT_ULL(reg_c);
+ if (needs_precise)
+ precise_classes |= BIT_ULL(reg_c);
abi |= PERF_SAMPLE_REGS_ABI_SIMD;
}
}
- if (pred)
+ if (pred) {
*out_pred_mask = supported_classes;
- else
+ pred_precise_mask = precise_classes;
+ } else {
*out_simd_mask = supported_classes;
+ simd_precise_mask = precise_classes;
+ }
}
if (!(abi & PERF_SAMPLE_REGS_ABI_SIMD)) {
@@ -3585,8 +3608,6 @@ static void probe_pmu_regs_one(const struct perf_pmu *pmu,
x_attr.disabled = 1;
x_attr.sample_period = base_attr->sample_period ?: 10000;
x_attr.sample_type = sample_type;
- if (intr && max_precise > 0)
- x_attr.precise_ip = 1;
if (ext_mask) {
if (intr)
@@ -3594,10 +3615,11 @@ static void probe_pmu_regs_one(const struct perf_pmu *pmu,
else
x_attr.sample_regs_user = ext_mask;
- fd = sys_perf_event_open(&x_attr, pid, cpu, -1, flags);
- if (fd >= 0) {
- close(fd);
+ if (probe_regs_open(&x_attr, pid, cpu, flags, try_precise,
+ &needs_precise)) {
mask |= ext_mask;
+ if (needs_precise)
+ precise_mask |= ext_mask;
batch_ok = true;
}
}
@@ -3610,10 +3632,11 @@ static void probe_pmu_regs_one(const struct perf_pmu *pmu,
x_attr.sample_regs_intr = BIT_ULL(b);
else
x_attr.sample_regs_user = BIT_ULL(b);
- fd = sys_perf_event_open(&x_attr, pid, cpu, -1, flags);
- if (fd >= 0) {
- close(fd);
+ if (probe_regs_open(&x_attr, pid, cpu, flags, try_precise,
+ &needs_precise)) {
mask |= BIT_ULL(b);
+ if (needs_precise)
+ precise_mask |= BIT_ULL(b);
}
}
}
@@ -3621,6 +3644,12 @@ static void probe_pmu_regs_one(const struct perf_pmu *pmu,
*out_mask = mask;
*out_abi = abi;
+ if (out_precise_mask)
+ *out_precise_mask = precise_mask;
+ if (out_simd_precise_mask)
+ *out_simd_precise_mask = simd_precise_mask;
+ if (out_pred_precise_mask)
+ *out_pred_precise_mask = pred_precise_mask;
}
/*
@@ -4027,7 +4056,10 @@ static void __perf_pmu__probe(struct perf_pmu *pmu, int pmu_cpu)
&pmu->probed.user_regs_mask,
&pmu->probed.user_regs_abi,
&pmu->probed.user_simd_mask,
- &pmu->probed.user_pred_mask);
+ &pmu->probed.user_pred_mask,
+ /*out_precise_mask=*/NULL,
+ /*out_simd_precise_mask=*/NULL,
+ /*out_pred_precise_mask=*/NULL);
}
if (pmu->probed.sample_types & PERF_SAMPLE_REGS_INTR) {
probe_pmu_regs_one(pmu, &base_attr, pid, cpu, flags,
@@ -4035,7 +4067,10 @@ static void __perf_pmu__probe(struct perf_pmu *pmu, int pmu_cpu)
&pmu->probed.intr_regs_mask,
&pmu->probed.intr_regs_abi,
&pmu->probed.intr_simd_mask,
- &pmu->probed.intr_pred_mask);
+ &pmu->probed.intr_pred_mask,
+ &pmu->probed.intr_regs_precise_mask,
+ &pmu->probed.intr_simd_precise_mask,
+ &pmu->probed.intr_pred_precise_mask);
}
/* 4. Privilege / exclusion modifiers */
diff --git a/tools/perf/util/pmu.h b/tools/perf/util/pmu.h
index 66ee3841872a..21c4b1a4b608 100644
--- a/tools/perf/util/pmu.h
+++ b/tools/perf/util/pmu.h
@@ -333,6 +333,22 @@ struct perf_pmu {
* register classes.
*/
u64 intr_pred_mask;
+ /**
+ * @probed.intr_regs_precise_mask: Subset of intr_regs_mask that
+ * can only be sampled with precise sampling, such as x86 XMM
+ * registers that are captured by PEBS.
+ */
+ u64 intr_regs_precise_mask;
+ /**
+ * @probed.intr_simd_precise_mask: Subset of intr_simd_mask that
+ * can only be sampled with precise sampling.
+ */
+ u64 intr_simd_precise_mask;
+ /**
+ * @probed.intr_pred_precise_mask: Subset of intr_pred_mask that
+ * can only be sampled with precise sampling.
+ */
+ u64 intr_pred_precise_mask;
} probed;
};
--
2.56.1.703.gf848ed807c-goog
next prev parent reply other threads:[~2026-11-13 19:56 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-13 19:55 [PATCH v2 00/16] perf sysinfo: Add subcommand to probe and summarize PMU capabilities Ian Rogers
2026-11-13 19:55 ` [PATCH v2 01/16] perf pmus: Expose duplicate uncore PMU scanning helpers Ian Rogers
2026-11-13 19:55 ` [PATCH v2 02/16] perf mem-events: Expose PMU init and name formatting helpers Ian Rogers
2026-11-13 19:55 ` [PATCH v2 03/16] perf pmu: Add perf_pmu__probe() for basic open, counting, and sampling Ian Rogers
2026-11-13 19:55 ` [PATCH v2 04/16] perf pmu: Probe supported sample_type flags Ian Rogers
2026-11-13 19:55 ` [PATCH v2 05/16] perf pmu: Probe precise_ip levels Ian Rogers
2026-11-13 19:55 ` [PATCH v2 06/16] perf pmu: Probe privilege exclusion modifiers Ian Rogers
2026-11-13 19:55 ` [PATCH v2 07/16] perf pmu: Probe execution and AUX area features Ian Rogers
2026-11-13 19:55 ` [PATCH v2 08/16] perf pmu: Probe event group size limits Ian Rogers
2026-11-13 19:55 ` [PATCH v2 09/16] perf pmu: Probe user and interrupt sample register masks Ian Rogers
2026-11-13 19:55 ` Ian Rogers [this message]
2026-11-13 19:55 ` [PATCH v2 11/16] perf pmu: Probe memory profiling events and sample formats Ian Rogers
2026-11-13 19:55 ` [PATCH v2 12/16] perf pmu: Probe user-space mmap capabilities Ian Rogers
2026-11-13 19:55 ` [PATCH v2 13/16] perf pmu: Probe branch instruction skid Ian Rogers
2026-11-13 19:55 ` [PATCH v2 14/16] perf sysinfo: Add sysinfo subcommand Ian Rogers
2026-11-13 19:56 ` [PATCH v2 15/16] perf docs: Add perf-sysinfo man page Ian Rogers
2026-11-13 19:56 ` [PATCH v2 16/16] perf test: Add perf sysinfo shell test Ian Rogers
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20261113195601.2872738-11-irogers@google.com \
--to=irogers@google.com \
--cc=acme@kernel.org \
--cc=adrian.hunter@intel.com \
--cc=james.clark@linaro.org \
--cc=jolsa@kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-perf-users@vger.kernel.org \
--cc=mingo@redhat.com \
--cc=namhyung@kernel.org \
--cc=peterz@infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®