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charset="utf-8" Message-Id: <20261114-b4-cs75xx-v7-8-8f17f38821b4@gmail.com> References: <20261114-b4-cs75xx-v7-0-8f17f38821b4@gmail.com> In-Reply-To: <20261114-b4-cs75xx-v7-0-8f17f38821b4@gmail.com> To: Arnd Bergmann , Linus Walleij , Krzysztof Kozlowski Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , Jiri Slaby , Russell King , Alexandre Belloni , Drew Fustini , Lorenzo Pieralisi , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, Jason Li , Fil Dunsky X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1794663665; l=6235; i=filipp.dunsky@gmail.com; s=20260930; h=from:subject:message-id; bh=n/Dq4py/0eGRBnmQUzS6IOXN56dx/13Os1x5nNKfay0=; b=fq2JIa474ARBkTYrUpi/6SUkTPx9EkieRQk4ocvQ+6BQYH2CimOsg945UXP+Emv1vwdR8rhau mQMNh8++legDTnfDt5kV5TtrTOU1GW5JcoMHbN+fIBtsxTP8wpZkMNM X-Developer-Key: i=filipp.dunsky@gmail.com; a=ed25519; pk=JAYP8e2rJ54DHOmhNtXud8rl1igAaAXoOHxtJmVXI1g= X-Endpoint-Received: by B4 Relay for filipp.dunsky@gmail.com/20260930 with auth_id=1085 X-Original-From: Fil Dunsky Reply-To: filipp.dunsky@gmail.com Content-Transfer-Encoding: 7bit From: Fil Dunsky Add a minimal description of the Cortina Systems CS7542 SoC: the two Cortex-A9 cores, SCU, GIC, global timer, private timer and watchdog, PL310 L2 cache controller and the four on-chip UARTs. The peripheral clock (APB) runs at 100, 150 or 170 MHz depending on the boot strap pins. Until there is a driver for the global control block that reads the straps, model it as a fixed clock whose rate is provided by the board. The Securifi Almond+ is a touchscreen Wi-Fi router with 512 MiB of DDR3, 512 MiB of NAND flash, a QCA8337 switch, QCA9880 and AR9580 Wi-Fi and an ASM1042 USB 3.0 controller behind the SoC PCIe root ports. For now, describe the memory and the console UART, and reserve the top 64 MiB of RAM which the vendor firmware hands to the packet engine queue manager. Reviewed-by: Linus Walleij Signed-off-by: Fil Dunsky --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/cortina/Makefile | 3 + .../dts/cortina/cs7542-securifi-almondplus.dts | 46 ++++++++ arch/arm/boot/dts/cortina/cs7542.dtsi | 127 +++++++++++++++++++++ 4 files changed, 177 insertions(+) diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 28fba538d..cf4433001 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -12,6 +12,7 @@ subdir-y += broadcom subdir-y += calxeda subdir-y += cirrus subdir-y += cnxt +subdir-y += cortina subdir-y += gemini subdir-y += hisilicon subdir-y += hpe diff --git a/arch/arm/boot/dts/cortina/Makefile b/arch/arm/boot/dts/cortina/Makefile new file mode 100644 index 000000000..93be6c9ae --- /dev/null +++ b/arch/arm/boot/dts/cortina/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_CORTINA_ACCESS) += \ + cs7542-securifi-almondplus.dtb diff --git a/arch/arm/boot/dts/cortina/cs7542-securifi-almondplus.dts b/arch/arm/boot/dts/cortina/cs7542-securifi-almondplus.dts new file mode 100644 index 000000000..e3152fd1d --- /dev/null +++ b/arch/arm/boot/dts/cortina/cs7542-securifi-almondplus.dts @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Device Tree Source for the Securifi Almond+ router + */ + +/dts-v1/; + +#include "cs7542.dtsi" + +/ { + model = "Securifi Almond+"; + compatible = "securifi,almondplus", "cortina,cs7542"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + reserved-memory { + ranges; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserved for the packet engine queue manager */ + qm-buffer@1c000000 { + reg = <0x1c000000 0x4000000>; + no-map; + }; + }; +}; + +&apb_clk { + clock-frequency = <150000000>; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/cortina/cs7542.dtsi b/arch/arm/boot/dts/cortina/cs7542.dtsi new file mode 100644 index 000000000..29b0b7da8 --- /dev/null +++ b/arch/arm/boot/dts/cortina/cs7542.dtsi @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Device Tree Source for the Cortina Systems CS7542 SoC + */ + +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + /* Rate is selected by the boot strap pins, set by the board */ + apb_clk: clock-apb { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "apb"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + next-level-cache = <&l2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + enable-method = "cortina,cs7542-smp"; + cpu-release-addr = <0 0xf00000b8>; + next-level-cache = <&l2>; + }; + }; + + soc { + compatible = "simple-bus"; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + uart0: serial@f0070110 { + compatible = "cortina,cs7542-uart"; + reg = <0xf0070110 0x30>; + interrupts = ; + clocks = <&apb_clk>; + + status = "disabled"; + }; + + uart1: serial@f0070140 { + compatible = "cortina,cs7542-uart"; + reg = <0xf0070140 0x30>; + interrupts = ; + clocks = <&apb_clk>; + + status = "disabled"; + }; + + uart2: serial@f0070170 { + compatible = "cortina,cs7542-uart"; + reg = <0xf0070170 0x30>; + interrupts = ; + clocks = <&apb_clk>; + + status = "disabled"; + }; + + uart3: serial@f00701a0 { + compatible = "cortina,cs7542-uart"; + reg = <0xf00701a0 0x30>; + interrupts = ; + clocks = <&apb_clk>; + + status = "disabled"; + }; + + l2: cache-controller@f5010000 { + compatible = "arm,pl310-cache"; + reg = <0xf5010000 0x1000>; + cache-unified; + cache-level = <2>; + arm,shared-override; + arm,tag-latency = <1 1 1>; + arm,data-latency = <1 1 2>; + }; + + scu@f8000000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xf8000000 0x100>; + }; + + timer@f8000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0xf8000200 0x20>; + interrupts = ; + clocks = <&apb_clk>; + }; + + timer@f8000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xf8000600 0x20>; + interrupts = ; + clocks = <&apb_clk>; + }; + + watchdog@f8000620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0xf8000620 0x20>; + interrupts = ; + clocks = <&apb_clk>; + }; + + gic: interrupt-controller@f8001000 { + compatible = "arm,cortex-a9-gic"; + reg = <0xf8001000 0x1000>, + <0xf8000100 0x100>; + #interrupt-cells = <3>; + interrupt-controller; + }; + }; +}; -- 2.53.0