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Signed-off-by: Krishna Chaitanya Chundru --- Changes in v3: - Rebased to tip. - Link to v2: https://patch.msgid.link/20261019-monaco_ep-v2-0-852cb9f5d012@oss.qualcomm.com Changes in v2: - dt-bindings: PCI: qcom-ep: Drop qcs8300 compatible from the standalone enum list(Krzysztof) - PCI: qcom-ep: Fix qcom_pcie_disable_resources() to tear down resources in strict LIFO order (phy -> clocks -> interconnect bandwidth), matching the enable path's error-unwind sequence. (Sashiko AI review) - arm64: qcom: monaco: Add reset-gpios and wake-gpios to the pcie0_ep and pcie1_ep nodes so the EP driver owns and correctly manages the PERST# and WAKE# lines; drop the output-low override from the wake-pins pinctrl state that was permanently asserting WAKE#. (Sashiko AI review) - phy: qcom: qmp-pcie: Reword commit message to clarify the new RX tuning sequence for the 16 GT/s x4 PHY is common to RC and EP modes, not EP-only. - Link to v1: https://patch.msgid.link/20260921-monaco_ep-v1-0-63c5282fb0db@oss.qualcomm.com --- Krishna Chaitanya Chundru (6): dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add qcs8300 16 GT/s PHY dt-bindings: PCI: qcom-ep: Add QCS8300 compatible phy: qcom: qmp-pcie: Add endpoint PHY configuration for QCS8300 PCI: qcom-ep: Set initial interconnect bandwidth before enabling clocks arm64: qcom: monaco: Fix pcie1_phy compatible to list qcs8300 first arm64: qcom: monaco: Add PCIe Endpoint nodes .../devicetree/bindings/pci/qcom,pcie-ep.yaml | 4 + .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 4 + arch/arm64/boot/dts/qcom/monaco.dtsi | 150 ++++++++++++++++++++- drivers/pci/controller/dwc/pcie-qcom-ep.c | 36 ++--- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 105 +++++++++++++++ 5 files changed, 280 insertions(+), 19 deletions(-) --- base-commit: d0cf0853ff6b71724a399a87ca028fc57be9ccca change-id: 20260918-monaco_ep-fb14fafd0ecc Best regards, -- Krishna Chaitanya Chundru