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charset="utf-8" Message-Id: <20261114-v861-v1-13-eb71ec3ee523@iscas.ac.cn> References: <20261114-v861-v1-0-eb71ec3ee523@iscas.ac.cn> In-Reply-To: <20261114-v861-v1-0-eb71ec3ee523@iscas.ac.cn> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Guo Ren , Thomas Gleixner , Radu Rendec , Samuel Holland , Daniel Lezcano , Anup Patel , Han Gao , Stephen Boyd , Brian Masney , Jerome Brunet , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel , Alexandre Belloni , Maxime Ripard , Linus Walleij , Andre Przywara Cc: Han Gao , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , Conor Dooley , devicetree@vger.kernel.org, linux-csky@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rtc@vger.kernel.org, linux-gpio@vger.kernel.org X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1794609209; l=1288; i=gaohan@iscas.ac.cn; s=20261021; h=from:subject:message-id; bh=Q5nKbDPfL5bIJRudVipL8eRl+Sf6kVk4l+UGPGRoSrU=; b=grvbJPn/+R2MO+DEgByDUFTZtLVCqIBwHkLAL0ulBtY+dR3+FlP1mIhHsm4whuN7dLMvBp/6p +ihd2LdEuONA/g6geIuOhI8/hEPyOVjToZchKiHiT7GGOnYmqJ2XUOA X-Developer-Key: i=gaohan@iscas.ac.cn; a=ed25519; pk=J8WHEK3filS86QaCaIHDGafqhxKyQ4K7+vFgRirTIiY= X-Endpoint-Received: by B4 Relay for gaohan@iscas.ac.cn/20261021 with auth_id=1262 X-Original-From: Han Gao Reply-To: gaohan@iscas.ac.cn Content-Transfer-Encoding: 7bit From: Han Gao The V861 always-on pin controller has its interrupt registers at 0x40 instead of 0x200. Let the descriptor override the base. Signed-off-by: Han Gao --- drivers/pinctrl/sunxi/pinctrl-sunxi.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h index 7c2f29e75519..a0f5eac5c914 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -152,6 +152,11 @@ struct sunxi_pinctrl_desc { unsigned pin_base; unsigned irq_banks; const unsigned int *irq_bank_map; + /* + * Interrupt register base, where zero selects the traditional 0x200. + * Not used with the NCAT3 register layout. + */ + u32 irq_reg_base; bool irq_read_needs_mux; bool disable_strict_mode; enum sunxi_desc_bias_voltage io_bias_cfg_variant; @@ -261,7 +266,7 @@ static inline u32 sunxi_irq_base_reg(const struct sunxi_pinctrl *pctl, u16 bank) return pctl->bank_offset + bank * pctl->bank_mem_size + A733_IRQ_REGS_OFFSET; - return IRQ_REGS_OFFSET + + return (pctl->desc->irq_reg_base ?: IRQ_REGS_OFFSET) + sunxi_irq_hw_bank_num(pctl->desc, bank) * IRQ_MEM_SIZE; } -- 2.55.0