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[178.126.219.156]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c5095b5a4c1sm161402666b.48.2026.11.13.17.43.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Nov 2026 17:44:00 -0800 (PST) From: ElXreno To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@linux.intel.com, rodrigo.vivi@intel.com, joonas.lahtinen@linux.intel.com, tursulin@ursulin.net, ville.syrjala@linux.intel.com, ankit.k.nautiyal@intel.com, mitulkumar.ajitkumar.golani@intel.com, airlied@gmail.com, simona@ffwll.ch, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, ElXreno Subject: [PATCH 4/7] drm/i915: Split intel_update_crtc() into its stages Date: Sat, 14 Nov 2026 04:43:32 +0300 Message-ID: <20261114014335.2132756-5-elxreno@gmail.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261114014335.2132756-1-elxreno@gmail.com> References: <20261114014335.2132756-1-elxreno@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Pull the arming of a pipe on the MMIO path and the bookkeeping that follows the commit of a pipe out of intel_update_crtc(), into commit_pipe_arm() and intel_post_update_crtc(). The next patch arms several joined pipes inside one vblank evasion critical section and needs them separately. No functional change. Signed-off-by: ElXreno --- drivers/gpu/drm/i915/display/intel_display.c | 82 ++++++++++++-------- 1 file changed, 50 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 20b1103e3de4..aa03f674d93b 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7087,46 +7087,29 @@ static void intel_pre_update_crtc(struct intel_atomic_state *state, } } -static void intel_update_crtc(struct intel_atomic_state *state, - struct intel_crtc *crtc) +static void commit_pipe_arm(struct intel_atomic_state *state, + struct intel_crtc *crtc) { - const struct intel_crtc_state *old_crtc_state = - intel_atomic_get_old_crtc_state(state, crtc); - struct intel_crtc_state *new_crtc_state = + const struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - switch (new_crtc_state->commit_type) { - case INTEL_COMMIT_FLIPQ: - intel_flipq_enable(new_crtc_state); - - intel_crtc_prepare_vblank_event(new_crtc_state, &crtc->flipq_event); - - intel_flipq_add(crtc, INTEL_FLIPQ_PLANE_1, 0, INTEL_DSB_0, - new_crtc_state->dsb_commit); - break; - - case INTEL_COMMIT_DSB: - intel_crtc_prepare_vblank_event(new_crtc_state, &crtc->dsb_event); - + if (new_crtc_state->dsb_commit) intel_dsb_commit(new_crtc_state->dsb_commit); - break; - case INTEL_COMMIT_MMIO: - /* Perform vblank evasion around commit operation */ - intel_pipe_update_start(state, crtc); - - if (new_crtc_state->dsb_commit) - intel_dsb_commit(new_crtc_state->dsb_commit); + commit_pipe_pre_planes(state, crtc); - commit_pipe_pre_planes(state, crtc); + intel_crtc_planes_update_arm(NULL, state, crtc); - intel_crtc_planes_update_arm(NULL, state, crtc); - - commit_pipe_post_planes(state, crtc); + commit_pipe_post_planes(state, crtc); +} - intel_pipe_update_end(state, crtc); - break; - } +static void intel_post_update_crtc(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ + const struct intel_crtc_state *old_crtc_state = + intel_atomic_get_old_crtc_state(state, crtc); + struct intel_crtc_state *new_crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); /* * VRR/Seamless M/N update may need to update frame timings. @@ -7168,6 +7151,41 @@ static void intel_update_crtc(struct intel_atomic_state *state, } } +static void intel_update_crtc(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ + struct intel_crtc_state *new_crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); + + switch (new_crtc_state->commit_type) { + case INTEL_COMMIT_FLIPQ: + intel_flipq_enable(new_crtc_state); + + intel_crtc_prepare_vblank_event(new_crtc_state, &crtc->flipq_event); + + intel_flipq_add(crtc, INTEL_FLIPQ_PLANE_1, 0, INTEL_DSB_0, + new_crtc_state->dsb_commit); + break; + + case INTEL_COMMIT_DSB: + intel_crtc_prepare_vblank_event(new_crtc_state, &crtc->dsb_event); + + intel_dsb_commit(new_crtc_state->dsb_commit); + break; + + case INTEL_COMMIT_MMIO: + /* Perform vblank evasion around commit operation */ + intel_pipe_update_start(state, crtc); + + commit_pipe_arm(state, crtc); + + intel_pipe_update_end(state, crtc); + break; + } + + intel_post_update_crtc(state, crtc); +} + static void intel_old_crtc_state_disables(struct intel_atomic_state *state, struct intel_crtc *crtc) { -- 2.56.0