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As discussed there this does not work on arm64, and Ben and Reinette suggested to enhance the CMT test with a forgiving check instead. This series does that without needing a cache flush. Patch 1 fixes the CMT test failing when all cache bits are tested. Patch 2 measures a second time with all CBM bits set while the same benchmark keeps running, and checks that LLC occupancy increased by more than 15%. Tested on one MPAM system (16 bit CBM, 172 MB L3). - Default (5 bits) and -n 2, 4, 8: occupancy increases by 75% to 130% with the wider CBM, test passes. - -n 9 and -n 16: second measurement is skipped, test passes. -n 16 fails without patch 1 (write of "L3:1=0" fails). - With the second schemata write changed to not widen the CBM the new check fails as it should. Widening 8 bits to 9 (+11%) fails, to 10 (+23%) passes. - -n 1 fails the existing check with and without this series, occupancy is 35% below the expected value on this system. - The CMT test takes about 5 seconds longer. Changes since v5: - Drop "Implement cl_flus() and sb() for aarch64", replaced by patch 2. - Add patch 1. - "Recognise aarch64 as a vendor for L3_NONCONT_CAT" is sent separately, it does not depend on this series. [1] https://lore.kernel.org/r/20261012074729.40042-1-icheng@nvidia.com Richard Cheng (2): selftests/resctrl: Fix CMT test failure when all cache bits are tested selftests/resctrl: Check that CBM limits LLC occupancy in CMT test tools/testing/selftests/resctrl/cmt_test.c | 85 +++++++++++++++++++--- 1 file changed, 73 insertions(+), 12 deletions(-) base-commit: 30af56a227e27b892d34bc44c23298b5274913e3 -- 2.43.0