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[174.29.1.49]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-71ae860ebd7sm1145321eaf.8.2026.11.14.23.19.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 Nov 2026 23:19:47 -0800 (PST) From: James Hilliard Date: Sun, 15 Nov 2026 00:19:39 -0700 Subject: [PATCH v7 06/10] dmaengine: dw: simplify transfer-complete handling X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261115-submit-dw-dma-synchronize-v1-v7-6-8d58f3d49e4d@gmail.com> References: <20261115-submit-dw-dma-synchronize-v1-v7-0-8d58f3d49e4d@gmail.com> In-Reply-To: <20261115-submit-dw-dma-synchronize-v1-v7-0-8d58f3d49e4d@gmail.com> To: Viresh Kumar , Andy Shevchenko , Vinod Koul , Frank Li , Dan Williams Cc: Serge Semin , Greg Kroah-Hartman , Jiri Slaby , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , dmaengine@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org, Sashiko , Lars-Peter Clausen , James Hilliard , Frank Li X-Mailer: b4 0.15.2 With hardware-LLP residue handled by the status getter, the descriptor scanner only needs to process transfer-complete events. Return through a common unlock path when no event or active descriptor remains, and flatten the completion handling. Only one transaction is active on a channel. Detach that descriptor before starting the next queued transfer, keeping cookie completion under the channel lock and client notification outside it. Preserve software-LLP block advancement before completing the transaction. Reviewed-by: Frank Li Signed-off-by: James Hilliard --- drivers/dma/dw/core.c | 92 +++++++++++++++++++++------------------------------ 1 file changed, 38 insertions(+), 54 deletions(-) diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c index d9127337c849..3cc8579f8829 100644 --- a/drivers/dma/dw/core.c +++ b/drivers/dma/dw/core.c @@ -297,74 +297,58 @@ static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) { struct dw_desc *desc, *_desc; struct dw_desc *child; - u32 status_xfer; unsigned long flags; LIST_HEAD(list); spin_lock_irqsave(&dwc->lock, flags); - status_xfer = dma_readl(dw, RAW.XFER); - - if (status_xfer & dwc->mask) { - /* Everything we've submitted is done */ - dma_writel(dw, CLEAR.XFER, dwc->mask); - if (list_empty(&dwc->active_list)) { - spin_unlock_irqrestore(&dwc->lock, flags); - return; - } - - if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { - struct list_head *head, *active = dwc->tx_node_active; - - /* - * We are inside first active descriptor. - * Otherwise something is really wrong. - */ - desc = dwc_first_active(dwc); - - head = &desc->tx_list; - if (active != head) { - /* Update residue to reflect last sent descriptor */ - if (active == head->next) - desc->residue -= desc->len; - else - desc->residue -= to_dw_desc(active->prev)->len; - child = to_dw_desc(active); - - /* Submit next block */ - dwc_do_single_block(dwc, child); + if (!(dma_readl(dw, RAW.XFER) & dwc->mask)) + goto unlock; - spin_unlock_irqrestore(&dwc->lock, flags); - return; - } + dma_writel(dw, CLEAR.XFER, dwc->mask); + if (list_empty(&dwc->active_list)) + goto unlock; - /* We are done here */ - clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); + desc = dwc_first_active(dwc); + if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { + struct list_head *head = &desc->tx_list; + struct list_head *active = dwc->tx_node_active; + + if (active != head) { + /* Update residue to reflect last sent descriptor. */ + if (active == head->next) + desc->residue -= desc->len; + else + desc->residue -= to_dw_desc(active->prev)->len; + + child = to_dw_desc(active); + + /* Submit next block, including for polled transfers. */ + dwc_do_single_block(dwc, child); + goto unlock; } - if (dma_readl(dw, CH_EN) & dwc->mask) { - dev_err(dmaengine_chan_dev(&dwc->chan), - "BUG: XFER bit set, but channel not idle!\n"); - - /* Try to continue after resetting the channel... */ - dwc_chan_disable(dw, dwc); - } + clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); + } - /* Detach the completed transfer before starting queued work. */ - list_splice_init(&dwc->active_list, &list); - list_for_each_entry(desc, &list, desc_node) - dma_cookie_complete(&desc->txd); - dwc_dostart_first_queued(dwc); - spin_unlock_irqrestore(&dwc->lock, flags); + if (dma_readl(dw, CH_EN) & dwc->mask) { + dev_err(dmaengine_chan_dev(&dwc->chan), + "BUG: XFER bit set, but channel not idle!\n"); - list_for_each_entry_safe(desc, _desc, &list, desc_node) { - list_del_init(&desc->desc_node); - dwc_descriptor_free(dwc, desc, true); - } - return; + /* Try to continue after resetting the channel... */ + dwc_chan_disable(dw, dwc); } + dma_cookie_complete(&desc->txd); + list_move_tail(&desc->desc_node, &list); + dwc_dostart_first_queued(dwc); +unlock: spin_unlock_irqrestore(&dwc->lock, flags); + + list_for_each_entry_safe(desc, _desc, &list, desc_node) { + list_del_init(&desc->desc_node); + dwc_descriptor_free(dwc, desc, true); + } } static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_desc *desc) -- 2.53.0